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Features
* Fast, Extended Block RAM, 1.8 V FPGA Family - 560 Kb and 1,120 Kb embedded block RAM - 130 MHz internal performance (four LUT levels) - PCI compliant 3.3 V, 32/64-bit, 33/66-MHz Sophisticated SelectRAM+TM Memory Hierarchy - 294 Kb of internal configurable distributed RAM - Up to 1,120 Kb of synchronous internal block RAM - True Dual-Port block RAM - Memory bandwidth up to 2.24 Tb/s (equivalent bandwidth of over 100 RAMBUS channels) - Designed for high-performance Interfaces to external memories * 200 MHz ZBT* SRAMs * 200 Mb/s DDR SDRAMs Highly Flexible SelectIO+TM Technology - Supports 20 high-performance interface standards - Up to 556 singled-ended I/Os or up to 201 differential I/O pairs for an aggregate bandwidth of >100 Gb/s Complete Industry-Standard Differential Signalling Support - LVDS (622 Mb/s), BLVDS (Bus LVDS), LVPECL - Al I/O signals can be input, output, or bi-directional
* ZBT is a trademark of Integrated Device Technology, Inc.
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LVPECL and LVDS clock inputs for 300+ MHz clocks Proprietary High-Performance SelectLinkTM Technology - 80 Gb/s chip-to-chip communication link - Support for Double Data Rate (DDR) interface - Web-based HDL generation methodology Eight Fully Digital Delay-Locked Loops (DLLs) IEEE 1149.1 boundary-scan logic Supported by Xilinx Foundation SeriesTM and Alliance SeriesTM Development Systems - Internet Team Design (Xilinx iTDTM) tool ideal for million-plus gate density designs - Wide selection of PC or workstation platforms SRAM-based In-System Configuration - Unlimited re-programmability Advanced Packaging Options - 1.0 mm FG676 and FG900 - 1.27 mm BG560 0.18 m 6-layer Metal Process with Copper Interconnect 100% Factory Tested
Introduction
The VirtexTM-E Extended Memory (Virtex-EM) family of FPGAs is an extension of the highly successful Virtex-E family architecture. The Virtex-EM family (devices shown in Table 1) includes all of the features of Virtex-E, plus additional block RAM, useful for applications such as network switches and high-performance video graphic systems. Xilinx developed the Virtex-EM product family to enable customers to design systems requiring high memory bandwidth, such as 160 Gb/s network switches. Unlike traditional ASIC devices, this family also supports fast time-to-market delivery, because the development engineering is already completed. Just complete the design and program the device. There is no NRE, no silicon production cycles, and no additional delays for design re-work. In addition, designers can update the design over a network at any time, providing product upgrades or updates to customers even sooner. The Virtex-EM family is the result of more than fifteen years of FPGA design experience. Xilinx has a history of supporting customer applications by providing the highest level of logic, RAM, and features available in the industry. The Virtex-EM family, first FPGAs to deploy copper interconnect, offers the performance and high memory bandwidth for advanced system integration without the initial investment, long development cycles, and inventory risk expected in traditional ASIC development.
(c) 2000-2002 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm. All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
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Table 1: Virtex-E Extended Memory Field-Programmable Gate Array Family Members Device XCV405E XCV812E Logic Gates 129,600 254,016 CLB Array 40 x 60 56 x 84 Logic Cells 10,800 21,168 Differential I/O Pairs 183 201 User I/O 404 556 BlockRAM Bits 573,440 1,146,880 Distributed RAM Bits 153,600 301,056
Virtex-E Compared to Virtex Devices
The Virtex-E family offers up to 43,200 logic cells in devices up to 30% faster than the Virtex family. I/O performance is increased to 622 Mb/s using Source Synchronous data transmission architectures and synchronous system performance up to 240 MHz using singled-ended SelectI/O technology. Additional I/O standards are supported, notably LVPECL, LVDS, and BLVDS, which use two pins per signal. Almost all signal pins can be used for these new standards. Virtex-E devices have up to 640 Kb of faster (250MHz) block SelectRAM, but the individual RAMs are the same size and structure as in the Virtex family. They also have eight DLLs instead of the four in Virtex devices. Each individual DLL is slightly improved with easier clock mirroring and 4x frequency multiplication. VCCINT, the supply voltage for the internal logic and memory, is 1.8 V, instead of 2.5 V for Virtex devices. Advanced processing and 0.18 m design rules have resulted in smaller dice, faster speed, and lower power consumption. I/O pins are 3 V tolerant, and can be 5 V tolerant with an external 100 resistor. PCI 5 V is not supported. With the addition of appropriate external resistors, any pin can tolerate any voltage desired. Banking rules are different. With Virtex devices, all input buffers are powered by VCCINT. With Virtex-E devices, the LVTTL, LVCMOS2, and PCI input buffers are powered by the I/O supply voltage VCCO. The Virtex-E family is not bitstream-compatible with the Virtex family, but Virtex designs can be compiled into equivalent Virtex-E devices. The same device in the same package for the Virtex-E and Virtex families are pin-compatible with some minor exceptions. See the data sheet pinout section for details.
natives to mask-programmed gate arrays. The Virtex-E family includes the nine members in Table 1. Building on experience gained from Virtex FPGAs, the Virtex-E family is an evolutionary step forward in programmable logic design. Combining a wide variety of programmable system features, a rich hierarchy of fast, flexible interconnect resources, and advanced process technology, the Virtex-E family delivers a high-speed and high-capacity programmable logic solution that enhances design flexibility while reducing time-to-market.
Virtex-E Architecture
Virtex-E devices feature a flexible, regular architecture that comprises an array of configurable logic blocks (CLBs) surrounded by programmable input/output blocks (IOBs), all interconnected by a rich hierarchy of fast, versatile routing resources. The abundance of routing resources permits the Virtex-E family to accommodate even the largest and most complex designs. Virtex-E FPGAs are SRAM-based, and are customized by loading configuration data into internal memory cells. Configuration data can be read from an external SPROM (master serial mode), or can be written into the FPGA (SelectMAPTM, slave serial, and JTAG modes). The standard Xilinx Foundation SeriesTM and Alliance SeriesTM Development systems deliver complete design support for Virtex-E, covering every aspect from behavioral and schematic entry, through simulation, automatic design translation and implementation, to the creation and downloading of a configuration bit stream.
Higher Performance
Virtex-E devices provide better performance than previous generations of FPGAs. Designs can achieve synchronous system clock rates up to 240 MHz including I/O or 622 Mb/s using Source Synchronous data transmission architechtures. Virtex-E I/Os comply fully with 3.3 V PCI specifications, and interfaces can be implemented that operate at 33 MHz or 66 MHz. While performance is design-dependent, many designs operate internally at speeds in excess of 133 MHz and can achieve over 311 MHz. Table 2, page 3, shows performance data for representative circuits, using worst-case timing parameters.
General Description
The Virtex-E FPGA family delivers high-performance, high-capacity programmable logic solutions. Dramatic increases in silicon efficiency result from optimizing the new architecture for place-and-route efficiency and exploiting an aggressive 6-layer metal 0.18 m CMOS process. These advances make Virtex-E FPGAs powerful and flexible alter-
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VirtexTM-E 1.8 V Extended Memory Field Programmable Gate Arrays
Table 2: Performance for Common Circuit Functions Function
Register-to-Register
Bits
Virtex-E -7
Adder Pipelined Multiplier Address Decoder 16:1 Multiplexer Parity Tree
Chip-to-Chip
16 64 8x8 16 x 16 16 64
4.3 ns 6.3 ns 4.4 ns 5.1 ns 3.8 ns 5.5 ns 4.6 ns
9 18 36
3.5 ns 4.3 ns 5.9 ns
HSTL Class IV LVTTL,16mA, fast slew LVDS LVPECL
Virtex-E Extended Memory Device/Package Combinations and Maximum I/O
Table 3: Virtex-EM Family Maximum User I/O by Device/Package (Excluding Dedicated Clock Pins) Package BG560 FG676 FG900 XCV405E 404 404 556 XCV812E 404
Virtex-E Extended Memory Ordering Information
Example: XCV405E-6BG560C
Device Type Temperature Range C = Commercial (TJ = 0C to +85C) I = Industrial (TJ = -40C to +100C) Number of Pins Package Type BG = Ball Grid Array FG = Fine Pitch Ball Grid Array
DS025_001_112000
Speed Grade (-6, -7, -8)
Figure 1: Virtex Ordering Information
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Revision History
The following table shows the revision history for this document. Date 03/23/00 08/01/00 Version 1.0 1.1 Initial Xilinx release. Accumulated edits and fixes. Upgrade to Preliminary. Preview -8 numbers added. Reformatted to adhere to corporate documentation style guidelines. Minor changes in BG560 pin-out table. * * * * * * * 04/02/01 1.4 * * * 07/17/02 1.5 * In Table 3 (Module 4), FG676 Fine-Pitch BGA -- XCV405E, the following pins are no longer labeled as VREF: B7, G16, G26, W26, AF20, AF8, Y1, H1. Min values added to Virtex-E Electrical Characteristics tables. Updated speed grade -8 numbers in Virtex-E Electrical Characteristics tables (Module 3). Updated minimums in Table 11 (Module 2), and added notes to Table 12 (Module 2). Added to note 2 of Absolute Maximum Ratings (Module 3). Changed all minimum hold times to -0.4 for Global Clock Set-Up and Hold for LVTTL Standard, with DLL (Module 3). Revised maximum TDLLPW in -6 speed grade for DLL Timing Parameters (Module 3). In Table 4, FG676 Fine-Pitch BGA -- XCV405E, pin B19 is no longer labeled as VREF, and pin G16 is now labeled as VREF. Updated values in Virtex-E Switching Characteristics tables. Converted data sheet to modularized format. See Virtex-E Extended Memory Data Sheet, below. Data sheet designation upgraded from Preliminary to Production. Revision
09/19/00
1.2
11/20/00
1.3
Virtex-E Extended Memory Data Sheet
The Virtex-E Extended Memory Data Sheet contains the following modules: * * DS025-1, Virtex-E 1.8V Extended Memory FPGAs:
Introduction and Ordering Information (Module 1)
* *
DS025-3, Virtex-E 1.8V Extended Memory FPGAs:
DC and Switching Characteristics (Module 3)
DS025-2, Virtex-E 1.8V Extended Memory FPGAs:
Functional Description (Module 2)
DS025-4, Virtex-E 1.8V Extended Memory FPGAs:
Pinout Tables (Module 4)
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Architectural Description
Virtex-E Array
The Virtex-E user-programmable gate array (see Figure 1) comprises two major configurable elements: configurable logic blocks (CLBs) and input/output blocks (IOBs). * CLBs provide the functional elements for constructing logic. * IOBs provide the interface between the package pins and the CLBs. CLBs interconnect through a general routing matrix (GRM). The GRM comprises an array of routing switches located at the intersections of horizontal and vertical routing channels. Each CLB nests into a VersaBlockTM that also provides local routing resources to connect the CLB to the GRM. The VersaRingTM I/O interface provides additional routing resources around the periphery of the device. This routing improves I/O routability and facilitates pin locking. The Virtex-E architecture also includes the following circuits that connect to the GRM: * Dedicated block memories of 4096 bits each * Clock DLLs for clock-distribution delay compensation and clock domain control * 3-State buffers (BUFTs) associated with each CLB that drive dedicated segmentable horizontal routing resources
DLLDLL
DLLDLL
Values stored in static memory cells control the configurable logic elements and interconnect resources. These values load into the memory cells on power-up, and can reload if necessary to change the function of the device.
Input/Output Block
The Virtex-E IOB, Figure 2, features SelectIO+TM inputs and outputs that support a wide variety of I/O signalling standards (see Table 1).
DQ CE Weak Keeper SR
T TCE
O OCE
DQ CE
PAD OBUFT
SR I IQ Q Programmable Delay IBUF Vref SR SR CLK ICE
ds022_02_091300
D CE
Figure 2: Virtex-E Input/Output Block (IOB)
VersaRing
The three IOB storage elements function either as edge-triggered D-type flip-flops or as level-sensitive latches. Each IOB has a clock signal (CLK) shared by the three flip-flops and independent clock enable signals for each flip-flop.
BRAMs CLBs
BRAMs
BRAMs
BRAMs
CLBs
CLBs
CLBs
IOBs
IOBs
VersaRing
DLLDLL
DLLDLL
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Figure 1: Virtex-E Architecture Overview
(c) 2000-2002 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm. All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
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Input Path
Table 1: Supported I/O Standards Board Termination Voltage (VTT) N/A N/A N/A 1.50 1.25 1.20 1.50 0.75 1.50 1.50 N/A N/A N/A N/A N/A The Virtex-E IOB input path routes the input signal directly to internal logic and/ or through an optional input flip-flop. An optional delay element at the D-input of this flip-flop eliminates pad-to-pad hold time. The delay is matched to the internal clock-distribution delay of the FPGA, and when used, assures that the pad-to-pad hold time is zero. Each input buffer can be configured to conform to any of the low-voltage signalling standards supported. In some of these standards the input buffer utilizes a user-supplied threshold voltage, VREF. The need to supply VREF imposes constraints on which standards can be used in close proximity to each other. See "I/O Banking" on page 2. There are optional pull-up and pull-down resistors at each input for use after configuration. Their value is in the range 50 - 100 k.
I/O Standard LVTTL LVCMOS2 LVCMOS18 SSTL3 I & II SSTL2 I & II GTL GTL+ HSTL I HSTL III & IV CTT AGP-2X PCI33_3 PCI66_3 BLVDS & LVDS LVPECL
Output VCCO 3.3 2.5 1.8 3.3 2.5 N/A N/A 1.5 1.5 3.3 3.3 3.3 3.3 2.5 3.3
Input VCCO 3.3 2.5 1.8 N/A N/A N/A N/A N/A N/A N/A N/A 3.3 3.3 N/A N/A
Input VREF N/A N/A N/A 1.50 1.25 0.80 1.0 0.75 0.90 1.50 1.32 N/A N/A N/A N/A
Output Path
The output path includes a 3-state output buffer that drives the output signal onto the pad. The output signal can be routed to the buffer directly from the internal logic or through an optional IOB output flip-flop. The 3-state control of the output can also be routed directly from the internal logic or through a flip-flip that provides synchronous enable and disable. Each output driver can be individually programmed for a wide range of low-voltage signalling standards. Each output buffer can source up to 24 mA and sink up to 48 mA. Drive strength and slew rate controls minimize bus transients. In most signalling standards, the output High voltage depends on an externally supplied VCCO voltage. The need to supply VCCO imposes constraints on which standards can be used in close proximity to each other. See "I/O Banking" on page 2. An optional weak-keeper circuit is connected to each output. When selected, the circuit monitors the voltage on the pad and weakly drives the pin High or Low to match the input signal. If the pin is connected to a multiple-source signal, the weak keeper holds the signal in its last state if all drivers are disabled. Maintaining a valid logic level in this way eliminates bus chatter. Since the weak-keeper circuit uses the IOB input buffer to monitor the input level, an appropriate VREF voltage must be provided if the signalling standard requires one. The provision of this voltage must comply with the I/O banking rules.
In addition to the CLK and CE control signals, the three flip-flops share a Set/Reset (SR). For each flip-flop, this signal can be independently configured as a synchronous Set, a synchronous Reset, an asynchronous Preset, or an asynchronous Clear. The output buffer and all of the IOB control signals have independent polarity controls. All pads are protected against damage from electrostatic discharge (ESD) and from over-voltage transients. When PCI 3.3 V compliance is required, a conventional clamp diode is connected to the output supply voltage, VCCO. Optional pull-up, pull-down and weak-keeper circuits are attached to each pad. Prior to configuration all outputs not involved in configuration are forced into their high-impedance state. The pull-down resistors and the weak-keeper circuits are inactive, but IOs can optionally be pulled up. The activation of pull-up resistors prior to configuration is controlled on a global basis by the configuration mode pins. If the pull-up resistors are not activated, all the pins are in a high-impedance state. Consequently, external pull-up or pull-down resistors must be provided on pins required to be at a well-defined logic level prior to configuration. All Virtex-E IOBs support IEEE 1149.1-compatible boundary scan testing.
I/O Banking
Some of the I/O standards described above require VCCO and/or VREF voltages. These voltages are externally supplied and connected to device pins that serve groups of IOBs, called banks. Consequently, restrictions exist about which I/O standards can be combined within a given bank.
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VirtexTM-E 1.8 V Extended Memory Field Programmable Gate Arrays The VREF pins within a bank are interconnected internally and consequently only one VREF voltage can be used within each bank. All VREF pins in the bank, however, must be connected to the external voltage source for correct operation. Within a bank, inputs that require VREF can be mixed with those that do not. However, only one VREF voltage can be used within a bank. In Virtex-E, input buffers with LVTTL, LVCMOS2, LVCMOS18, PCI33_3, PCI66_3 standards are supplied by VCCO rather than VCCINT. For these standards, only input and output buffers that have the same VCCO can be mixed together. The VCCO and VREF pins for each bank appear in the device pin-out tables and diagrams. The diagrams also show the bank affiliation of each I/O. Within a given package, the number of VREF and VCCO pins can vary depending on the size of device. In larger devices, more I/O pins convert to VREF pins. Since these are always a super set of the VREF pins used for smaller devices, it is possible to design a PCB that permits migration to a larger device if necessary. All the VREF pins for the largest device anticipated must be connected to the VREF voltage, and not used for I/O. In smaller devices, some VCCO pins used in larger devices do not connect within the package. These unconnected pins can be left unconnected externally, or they can be connected to the VCCO voltage to permit migration to a larger device, if necessary.
Eight I/O banks result from separating each edge of the FPGA into two banks, as shown in Figure 3. Each bank has multiple VCCO pins, all of which must be connected to the same voltage. This voltage is determined by the output standards in use.
Bank 0 Bank 7 Bank 1 Bank 2
ds022_03_121799
GCLK3 GCLK2
VirtexE Device
Bank 6 GCLK1 GCLK0 Bank 5 Bank 4 Bank 3
Figure 3: Virtex-E I/O Banks Within a bank, output standards can be mixed only if they use the same VCCO. Compatible standards are shown in Table 2. GTL and GTL+ appear under all voltages because their open-drain outputs do not depend on VCCO. Table 2: VCCO 3.3 V 2.5 V 1.8 V 1.5 V Compatible Output Standards Compatible Standards PCI, LVTTL, SSTL3 I, SSTL3 II, CTT, AGP, GTL, GTL+, LVPECL SSTL2 I, SSTL2 II, LVCMOS2, GTL, GTL+, BLVDS, LVDS LVCMOS18, GTL, GTL+ HSTL I, HSTL III, HSTL IV, GTL, GTL+
Configurable Logic Block
The basic building block of the Virtex-E CLB is the logic cell (LC). An LC includes a 4-input function generator, carry logic, and a storage element. The output from the function generator in each LC drives both the CLB output and the D input of the flip-flop. Each Virtex-E CLB contains four LCs, organized in two similar slices, as shown in Figure 4. Figure 5 shows a more detailed view of a single slice.
Some input standards require a user-supplied threshold voltage, VREF. In this case, certain user-I/O pins are automatically configured as inputs for the VREF voltage. Approximately one in six of the I/O pins in the bank assume this role.
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COUT
COUT
G4 G3 G2 G1 RC LUT Carry & Control SP DQ CE
YB Y YQ
G4 G3 G2 G1 RC LUT Carry & Control SP DQ CE
YB Y YQ
BY
BY XB X
XB F4 F3 LUT F2 F1 RC Slice 0 Carry & Control SP DQ CE X XQ
F4 F3 F2 F1 LUT Carry & Control SP DQ CE
XQ
BX
RC Slice 1
BX
CIN
CIN
ds022_04_121799
Figure 4: 2-Slice Virtex-E CLB
COUT
YB CY G4 G3 G2 G1 I3 I2 I1 I0 LUT WE O DI INIT DQ CE REV XB F5IN F6 CY CK WE A4 BX F4 F3 F2 F1 I3 I2 I1 I0 WE LUT 0 1 SR CLK CE DI O REV WSO WSH BY DG BX DI INIT DQ CE F5 F5 X XQ Y YQ
0 1
BY
CIN
ds022_05_092000
Figure 5: Detailed View of Virtex-E Slice In addition to the four basic LCs, the Virtex-E CLB contains logic that combines function generators to provide functions of five or six inputs. Consequently, when estimating the number of system gates provided by a given device, each CLB counts as 4.5 LCs.
Look-Up Tables
Virtex-E function generators are implemented as 4-input look-up tables (LUTs). In addition to operating as a function generator, each LUT can provide a 16 x 1-bit synchronous RAM. Furthermore, the two LUTs within a slice can be com-
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bined to create a 16 x 2-bit or 32 x 1-bit synchronous RAM, or a 16 x 1-bit dual-port synchronous RAM. The Virtex-E LUT can also provide a 16-bit shift register that is ideal for capturing high-speed or burst-mode data. This mode can also be used to store data in applications such as Digital Signal Processing.
Arithmetic Logic
Dedicated carry logic provides fast arithmetic carry capability for high-speed arithmetic functions. The Virtex-E CLB supports two separate carry chains, one per Slice. The height of the carry chains is two bits per CLB. The arithmetic logic includes an XOR gate that allows a 2-bit full adder to be implemented within a slice. In addition, a dedicated AND gate improves the efficiency of multiplier implementation. The dedicated carry path can also be used to cascade function generators for implementing wide logic functions.
Storage Elements
The storage elements in the Virtex-E slice can be configured either as edge-triggered D-type flip-flops or as level-sensitive latches. The D inputs can be driven either by the function generators within the slice or directly from slice inputs, bypassing the function generators. In addition to Clock and Clock Enable signals, each Slice has synchronous set and reset signals (SR and BY). SR forces a storage element into the initialization state specified for it in the configuration. BY forces it into the opposite state. Alternatively, these signals can be configured to operate asynchronously. All of the control signals are independently invertible, and are shared by the two flip-flops within the slice.
BUFTs
Each Virtex-E CLB contains two 3-state drivers (BUFTs) that can drive on-chip busses. See "Dedicated Routing" on page 7. Each Virtex-E BUFT has an independent 3-state control pin and an independent input pin.
Block SelectRAM
Virtex-E FPGAs incorporate large block SelectRAM memories. These complement the Distributed SelectRAM memories that provide shallow RAM structures implemented in CLBs. Block SelectRAM memory blocks are organized in columns, starting at the left (column 0) and right outside edges and inserted every four CLB columns (see notes for smaller devices). Each memory block is four CLBs high, and each memory column extends the full height of the chip, immediately adjacent (to the right, except for column 0) of the CLB column locations indicated in Table 3.
Additional Logic
The F5 multiplexer in each slice combines the function generator outputs. This combination provides either a function generator that can implement any 5-input function, a 4:1 multiplexer, or selected functions of up to nine inputs. Similarly, the F6 multiplexer combines the outputs of all four function generators in the CLB by selecting one of the F5-multiplexer outputs. This permits the implementation of any 6-input function, an 8:1 multiplexer, or selected functions of up to 19 inputs. Each CLB has four direct feedthrough paths, two per slice. These paths provide extra data input lines or additional local routing that does not consume logic resources. Table 3: CLB/Block RAM Column Locations 0 48 12 16 20 24 28 32
Virtex-E Device XCV405E XCV812E
36
40
44
48
52
56
60
64
68
72
76
80
84

Table 4 shows the amount of block SelectRAM memory that is available in each Virtex-E device. Table 4: Virtex-E Block SelectRAM Amounts # of Blocks 140 280 Block SelectRAM Bits 573,440 1,146,880
Virtex-E Device XCV405E XCV812E
Each block SelectRAM cell, as illustrated in Figure 6, is a fully synchronous dual-ported (True Dual Port) 4096-bit RAM with independent control signals for each port. The data widths of the two ports can be configured independently, providing built-in bus-width conversion.
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WEA ENA RSTA CLKA ADDRA[#:0] DIA[#:0]
To Adjacent GRM
DOA[#:0]
To Adjacent GRM
GRM
To Adjacent GRM
WEB ENB RSTB CLKB ADDRB[#:0] DIB[#:0]
To Adjacent GRM
DOB[#:0]
Direct Connection To Adjacent CLB
CLB
Direct Connection To Adjacent CLB
XCVE_ds_007
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Figure 7: Virtex-E Local Routing
Figure 6: Dual-Port Block SelectRAM Table 5 shows the depth and width aspect ratios for the block SelectRAM. The Virtex-E block SelectRAM also includes dedicated routing to provide an efficient interface with both CLBs and other block SelectRAM modules. Table 5: Width 1 2 4 8 16 Block SelectRAM Port Aspect Ratios Depth 4096 2048 1024 512 256 ADDR Bus ADDR<11:0> ADDR<10:0> ADDR<9:0> ADDR<8:0> ADDR<7:0> Data Bus DATA<0> DATA<1:0> DATA<3:0> DATA<7:0> DATA<15:0>
General Purpose Routing
Most Virtex-E signals are routed on the general purpose routing, and consequently, the majority of interconnect resources are associated with this level of the routing hierarchy. The general routing resources are located in horizontal and vertical routing channels associated with the CLB rows and columns. The general-purpose routing resources are listed below. * Adjacent to each CLB is a General Routing Matrix (GRM). The GRM is the switch matrix through which horizontal and vertical routing resources connect, and is also the means by which the CLB gains access to the general purpose routing. 24 single-length lines route GRM signals to adjacent GRMs in each of the four directions. 72 buffered Hex lines route GRM signals to another GRMs six-blocks away in each one of the four directions. Organized in a staggered pattern, Hex lines are driven only at their endpoints. Hex-line signals can be accessed either at the endpoints or at the midpoint (three blocks from the source). One third of the Hex lines are bidirectional, while the remaining ones are uni-directional. 12 Longlines are buffered, bidirectional wires that distribute signals across the device quickly and efficiently. Vertical Longlines span the full height of the device, and horizontal ones span the full width of the device.
* *
Programmable Routing Matrix
It is the longest delay path that limits the speed of any worst-case design. Consequently, the Virtex-E routing architecture and its place-and-route software were defined in a joint optimization process. This joint optimization minimizes long-path delays, and consequently, yields the best system performance. The joint optimization also reduces design compilation times because the architecture is software-friendly. Design cycles are correspondingly reduced due to shorter design iteration times.
*
Local Routing
The VersaBlock, shown in Figure 7, provides local routing resources with the following types of connections: * * Interconnections among the LUTs, flip-flops, and GRM Internal CLB feedback paths that provide high-speed connections to LUTs within the same CLB, chaining them together with minimal routing delay Direct paths that provide high-speed connections between horizontally adjacent CLBs, eliminating the delay of the GRM
I/O Routing
Virtex-E devices have additional routing resources around their periphery that form an interface between the CLB array and the IOBs. This additional routing, called the VersaRing, facilitates pin-swapping and pin-locking, such that logic redesigns can adapt to existing PCB layouts. Time-to-market is reduced, since PCBs and other system components can be manufactured while the logic design is still in progress.
*
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VirtexTM-E 1.8 V Extended Memory Field Programmable Gate Arrays
Dedicated Routing
Some signal classes require dedicated routing resources to maximize performance. In the Virtex-E architecture, dedicated routing resources are provided for two signal classes. * Horizontal routing resources are provided for on-chip 3-state busses. Four partitionable bus lines are provided per CLB row, permitting multiple busses within a row, as shown in Figure 8. * Two dedicated nets per CLB propagate carry signals vertically to the adjacent CLB. Global Clock Distribution Network. DLL Location
*
Tri-State Lines
CLB
CLB
CLB
CLB
buft_c.eps
Figure 8: BUFT Connections to Dedicated Horizontal Bus LInes
Clock Routing
Clock Routing resources distribute clocks and other signals with very high fanout throughout the device. Virtex-E devices include two tiers of clock routing resources referred to as global and local clock routing resources. * The global routing resources are four dedicated global nets with dedicated input pins that are designed to distribute high-fanout clock signals with minimal skew. Each global clock net can drive all CLB, IOB, and block RAM clock pins. The global nets can be driven only by global buffers. There are four global buffers, one for each global net. * The local clock routing resources consist of 24 backbone lines, 12 across the top of the chip and 12 across bottom. From these lines, up to 12 unique signals per column can be distributed via the 12 longlines in the column. These local resources are more flexible than the global resources since they are not restricted to routing only to clock pins.
Global Clock Distribution
Virtex-E provides high-speed, low-skew clock distribution through the global routing resources described above. A typical clock distribution net is shown in Figure 9.
GCLKPAD3 GCLKBUF3 Global Clock Rows GCLKPAD2 GCLKBUF2 Global Clock Column
Four global buffers are provided, two at the top center of the device and two at the bottom center. These drive the four global nets that in turn drive any clock pin. Four dedicated clock pads are provided, one adjacent to each of the global buffers. The input to the global buffer is selected either from these pads or from signals in the general purpose routing.
Digital Delay-Locked Loops
There are eight DLLs (Delay-Locked Loops) per device, with four located at the top and four at the bottom, Figure 10. The DLLs can be used to eliminate skew between the clock input pad and the internal clock input pins throughout the device. Each DLL can drive two global clock networks.The DLL monitors the input clock and the distributed clock, and automatically adjusts a clock delay element. Additional delay is introduced such that clock edges arrive at internal flip-flops synchronized with clock edges arriving at the input. In addition to eliminating clock-distribution delay, the DLL provides advanced control of multiple clock domains. The
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Global Clock Spine
GCLKBUF1 GCLKPAD1
GCLKBUF0 GCLKPAD0
XCVE_009
Figure 9: Global Clock Distribution Network
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VirtexTM-E 1.8 V Extended Memory Field Programmable Gate Arrays DLL provides four quadrature phases of the source clock, and can double the clock or divide the clock by 1.5, 2, 2.5, 3, 4, 5, 8, or 16. The DLL also operates as a clock mirror. By driving the output from a DLL off-chip and then back on again, the DLL can be used to de-skew a board level clock among multiple devices. In order to guarantee that the system clock is operating correctly prior to the FPGA starting up after configuration, the DLL can delay the completion of the configuration process until after it has achieved lock. For more information about DLL functionality, see the Design Consideration section of the data sheet.
DLLDLL
DLLDLL
XCVE_0010
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DLLDLL
DLLDLL
Secondary DLLs
Secondary DLLs
Primary DLLs
Figure 10: DLL Locations
Boundary Scan
Virtex-E devices support all the mandatory boundary-scan instructions specified in the IEEE standard 1149.1. A Test Access Port (TAP) and registers are provided that implement the EXTEST, INTEST, SAMPLE/PRELOAD, BYPASS, IDCODE, USERCODE, and HIGHZ instructions. The TAP also supports two internal scan chains and configuration/readback of the device. The JTAG input pins (TDI, TMS, TCK) do not have a VCCO requirement, and operate with either 2.5 V or 3.3 V input signalling levels. The output pin (TDO) is sourced from the VCCO in bank 2, and for proper operation of LVTTL 3.3 V levels, the bank should be supplied with 3.3 V. Boundary-scan operation is independent of individual IOB configurations, and unaffected by package type. All IOBs, including un-bonded ones, are treated as independent 3-state bidirectional pins in a single scan chain. Retention of the bidirectional test capability after configuration facilitates the testing of external interconnections. Table 6 lists the boundary-scan instructions supported in Virtex-E FPGAs. Internal signals can be captured during EXTEST by connecting them to un-bonded or unused IOBs. They can also be connected to the unused outputs of IOBs defined as unidirectional input pins. Before the device is configured, all instructions except USER1 and USER2 are available. After configuration, all instructions are available. During configuration, it is recommended that those operations using the boundary-scan register (SAMPLE/PRELOAD, INTEST, EXTEST) not be performed. In addition to the test instructions outlined above, the boundary-scan circuitry can be used to configure the FPGA, and also to read back the configuration data.
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VirtexTM-E 1.8 V Extended Memory Field Programmable Gate Arrays
Figure 11 is a diagram of the Virtex-E Series boundary scan logic. It includes three bits of Data Register per IOB, the IEEE 1149.1 Test Access Port controller, and the Instruction Register with decodes.
DATA IN IOB.T 1 0 IOB IOB IOB IOB IOB D Q D sd Q 0 1
LE
IOB
IOB
1 0
sd D Q D Q
IOB
IOB LE
IOB
IOB IOB.I 1 0 1 sd D Q D Q
IOB
IOB
IOB
IOB
0
IOB
IOB
LE 1 IOB.Q IOB.T 0
IOB
BYPASS REGISTER INSTRUCTION REGISTER
IOB
TDI
M TDO U X
0 1 0 D Q D sd Q 1
LE
1 0 D Q D
sd Q
LE
1 IOB.I 0
DATAOUT SHIFT/ CLOCK DATA CAPTURE REGISTER
UPDATE
EXTEST
X9016
Figure 11: Virtex-E Family Boundary Scan Logic
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VirtexTM-E 1.8 V Extended Memory Field Programmable Gate Arrays Table 6: Boundary Scan Instructions Binary Code (4:0) 00000 00001 Description Enable boundary-scan EXTEST operation. Enable boundary-scan SAMPLE/PRELOAD operation. Access user-defined register 1. Access user-defined register 2. Access the configuration bus for read operations. Access the configuration bus for write operations. Enable boundary-scan INTEST operation. Enable shifting out USER code. Enable shifting out of ID Code. 3-state output pins while enabling the Bypass Register. Clock the start-up sequence when StartupClk is TCK. Enable BYPASS. Xilinx reserved instructions.
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Boundary-Scan Command EXTEST SAMPLE/ PRELOAD USER1 USER2 CFG_OUT
Each EXTEST CAPTURED-OR state captures all In, Out, and 3-state pins. The other standard data register is the single flip-flop BYPASS register. It synchronizes data being passed through the FPGA to the next downstream boundary scan device. The FPGA supports up to two additional internal scan chains that can be specified using the BSCAN macro. The macro provides two user pins (SEL1 and SEL2) which are decodes of the USER1 and USER2 instructions respectively. For these instructions, two corresponding pins (T DO1 and TDO2) allow user scan data to be shifted out of TDO. Likewise, there are individual clock pins (DRCK1 and DRCK2) for each user register. There is a common input pin (TDI) and shared output pins that represent the state of the TAP controller (RESET, SHIFT, and UPDATE).
00010 00011 00100
CFG_IN
00101
Bit Sequence
The order within each IOB is: In, Out, 3-State. The input-only pins contribute only the In bit to the boundary scan I/O data register, while the output-only pins contributes all three bits. From a cavity-up view of the chip (as shown in EPIC), starting in the upper right chip corner, the boundary scan data-register bits are ordered as shown in Figure 12. BSDL (Boundary Scan Description Language) files for Virtex-E Series devices are available on the Xilinx web site in the File Download area.
INTEST USERCODE IDCODE HIGHZ
00111 01000 01001 01010
JSTART
01100
Bit 0 ( TDO end) Bit 1 Bit 2
Right half of top-edge IOBs (Right to Left) GCLK2 GCLK3 Left half of top-edge IOBs (Right to Left) Left-edge IOBs (Top to Bottom) M1 M0 M2 Left half of bottom-edge IOBs (Left to Right) GCLK1 GCLK0 Right half of bottom-edge IOBs (Left to Right) DONE PROG Right-edge IOBs (Bottom to Top)
BYPASS RESERVED
11111 All other codes
Instruction Set
The Virtex-E Series boundary scan instruction set also includes instructions to configure the device and read back configuration data (CFG_IN, CFG_OUT, and JSTART). The complete instruction set is coded as shown in Table 6.
(TDI end)
CCLK
990602001
Data Registers
The primary data register is the boundary scan register. For each IOB pin in the FPGA, bonded or not, it includes three bits for In, Out, and 3-State Control. Non-IOB pins have appropriate partial bit population if input-only or output-only.
Figure 12: Boundary Scan Bit Sequence
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VirtexTM-E 1.8 V Extended Memory Field Programmable Gate Arrays Table 7: IDCODEs Assigned to Virtex-E FPGAs FPGA XCV405EM XCV812EM IDCODE v0C28093h v0C38093h
Identification Registers
The IDCODE register is supported. By using the IDCODE, the device connected to the JTAG port can be determined. The IDCODE register has the following binary format: vvvv:ffff:fffa:aaaa:aaaa:cccc:cccc:ccc1 where v = the die version number f = the family code (05 for Virtex-E family) a = the number of CLB rows (ranges from 16 for XCV50E to 104 for XCV3200E) c = the company code (49h for Xilinx) The USERCODE register is supported. By using the USERCODE, a user-programmable identification code can be loaded and shifted out for examination. The identification code (see Table 7) is embedded in the bitstream during bitstream generation and is valid only after configuration.
Note: Attempting to load an incorrect bitstream causes configuration to fail and can damage the device.
Including Boundary Scan in a Design
Since the boundary scan pins are dedicated, no special element needs to be added to the design unless an internal data register (USER1 or USER2) is desired. If an internal data register is used, insert the boundary scan symbol and connect the necessary pins as appropriate.
Development System
Virtex-E FPGAs are supported by the Xilinx Foundation and Alliance Series CAE tools. The basic methodology for Virtex-E design consists of three interrelated steps: design entry, implementation, and verification. Industry-standard tools are used for design entry and simulation (for example, Synopsys FPGA Express), while Xilinx provides proprietary architecture-specific tools for implementation. The Xilinx development system is integrated under the Xilinx Design Manager (XDMTM) software, providing designers with a common user interface regardless of their choice of entry and verification tools. The XDM software simplifies the selection of implementation options with pull-down menus and on-line help. Application programs ranging from schematic capture to Placement and Routing (PAR) can be accessed through the XDM software. The program command sequence is generated prior to execution, and stored for documentation. Several advanced software features facilitate Virtex-E design. RPMs, for example, are schematic-based macros with relative location constraints to guide their placement. They help ensure optimal implementation of common functions. For HDL design entry, the Xilinx FPGA Foundation development system provides interfaces to the following synthesis design environments. * * * Synopsys (FPGA Compiler, FPGA Express) Exemplar (Spectrum) Synplicity (Synplify) A standard interface-file specification, Electronic Design Interchange Format (EDIF), simplifies file transfers into and out of the development system. Virtex-E FPGAs are supported by a unified library of standard functions. This library contains over 400 primitives and macros, ranging from 2-input AND gates to 16-bit accumulators, and includes arithmetic functions, comparators, counters, data registers, decoders, encoders, I/O functions, latches, Boolean functions, multiplexers, shift registers, and barrel shifters. The "soft macro" portion of the library contains detailed descriptions of common logic functions, but does not contain any partitioning or placement information. The performance of these macros depends, therefore, on the partitioning and placement obtained during implementation. RPMs, on the other hand, do contain predetermined partitioning and placement information that permits optimal implementation of these functions. Users can create their own library of soft macros or RPMs based on the macros and primitives in the standard library. The design environment supports hierarchical design entry, with high-level schematics that comprise major functional blocks, while lower-level schematics define the logic in these blocks. These hierarchical design elements are automatically combined by the implementation tools. Different design entry tools can be combined within a hierarchical design, thus allowing the most convenient entry method to be used for each portion of the design.
For schematic design entry, the Xilinx FPGA Foundation and Alliance development system provides interfaces to the following schematic-capture design environments. * * Mentor Graphics V8 (Design Architect, QuickSim II) Viewlogic Systems (Viewdraw)
Design Implementation
The place-and-route tools (PAR) automatically provide the implementation flow described in this section. The partitioner takes the EDIF net list for the design and maps the logic into the architectural resources of the FPGA (CLBs and IOBs, for example). The placer then determines the best locations for these blocks based on their interconnecModule 2 of 4 11
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VirtexTM-E 1.8 V Extended Memory Field Programmable Gate Arrays tions and the desired performance. Finally, the router interconnects the blocks. The PAR algorithms support fully automatic implementation of most designs. For demanding applications, however, the user can exercise various degrees of control over the process. User partitioning, placement, and routing information is optionally specified during the design-entry process. The implementation of highly structured designs can benefit greatly from basic floor planning. The implementation software incorporates Timing Wizard(R) timing-driven placement and routing. Designers specify timing requirements along entire paths during design entry. The timing path analysis routines in PAR then recognize these user-specified requirements and accommodate them. Timing requirements are entered on a schematic in a form directly relating to the system requirements, such as the targeted clock frequency, or the maximum allowable delay between two registers. In this way, the overall performance of the system along entire signal paths is automatically tailored to user-generated specifications. Specific timing information for individual nets is unnecessary.
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Design Verification
In addition to conventional software simulation, FPGA users can use in-circuit debugging techniques. Because Xilinx devices are infinitely reprogrammable, designs can be verified in real time without the need for extensive sets of software simulation vectors. The development system supports both software simulation and in-circuit debugging techniques. For simulation, the system extracts the post-layout timing information from the design database, and back-annotates this information into the net list for use by the simulator. Alternatively, the user can verify timing-critical portions of the design using the TRCE(R) static timing analyzer. For in-circuit debugging, an optional download and readback cable is available. This cable connects the FPGA in the target system to a PC or workstation. After downloading the design into the FPGA, the designer can single-step the logic, readback the contents of the flip-flops, and so observe the internal logic state. Simple modifications can be downloaded into the system in a matter of minutes.
Configuration
Virtex-E devices are configured by loading configuration data into the internal configuration memory. Note that attempting to load an incorrect bitstream causes configuration to fail and can damage the device. Some of the pins used for configuration are dedicated pins, while others can be re-used as general purpose inputs and outputs once configuration is complete. The following are dedicated pins: * Mode pins (M2, M1, M0) * Configuration clock pin (CCLK) * PROGRAM pin * DONE pin * Boundary-scan pins (TDI, TDO, TMS, TCK) Depending on the configuration mode chosen, CCLK can be an output generated by the FPGA, or it can be generated externally and provided to the FPGA as an input. For correct operation, these pins require a VCCO of 3.3 V to permit LVTTL operation. All of the pins affected are in banks 2 or 3. Table 8: Configuration Codes M2 0 1 1 1 1 0 0 0 M1 0 0 1 1 0 0 1 1 M0 0 1 0 1 0 1 0 1 CCLK Direction Out N/A In In Out N/A In In Data Width 1 1 8 1 1 1 8 1 Serial Dout Yes No No Yes Yes No No Yes Configuration Pull-ups No No No No Yes Yes Yes Yes Configuration Mode Master-serial mode Boundary-scan mode SelectMAP mode Slave-serial mode Master-serial mode Boundary-scan mode SelectMAP mode Slave-serial mode
Configuration Modes
Virtex-E supports the following four configuration modes. * Slave-serial mode * Master-serial mode * SelectMAP mode * Boundary-scan mode (JTAG) The Configuration mode pins (M2, M1, M0) select among these configuration modes with the option in each case of having the IOB pins either pulled up or left floating prior to configuration. The selection codes are listed in Table 8. Configuration through the boundary-scan port is always available, independent of the mode selection. Selecting the boundary-scan mode simply turns off the other modes. The three mode pins have internal pull-up resistors, and default to a logic High if left unconnected.
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VirtexTM-E 1.8 V Extended Memory Field Programmable Gate Arrays ured, the data for the next device is routed to the DOUT pin. Data on the DOUT pin changes on the rising edge of CCLK. The change of DOUT on the rising edge of CCLK differs from previous families but does not cause a problem for mixed configuration chains. This change was made to improve serial configuration rates for Virtex and Virtex-E only chains. Figure 13 shows a full master/slave system. A Virtex-E device in slave-serial mode should be connected as shown in the right-most device. Slave-serial mode is selected by applying <111> or <011> to the mode pins (M2, M1, M0). A weak pull-up on the mode pins makes slave-serial the default mode if the pins are left unconnected. Figure 14 shows slave-serial configuration timing. Table 10 provides more detail about the characteristics shown in Figure 14. Configuration must be delayed until the INIT pins of all daisy-chained FPGAs are High.
Table 9 lists the total number of bits required to configure each device. Table 9: Virtex-E Bitstream Lengths # of Configuration Bits 3,430,400 6,519,648
Device XCV405E XCV812E
Slave-Serial Mode
In slave-serial mode, the FPGA receives configuration data in bit-serial form from a serial PROM or other source of serial configuration data. The serial bitstream must be set up at the DIN input pin a short time before each rising edge of an externally generated CCLK. For more information on serial PROMs, see the PROM data sheet at http://www.xilinx.com/partinfo/ds026.pdf. Multiple FPGAs can be daisy-chained for configuration from a single source. After a particular FPGA has been configTable 10:
Master/Slave Serial Mode Programming Switching Description Figure References
1/2 1/2 3 4 5
Symbol
TDCC/TCCD TDSCK/TCKDS TCCO TCCH TCCL FCC
Values
5.0/0.0 5.0/0.0 12.0 5.0 5.0 66 +45% -30%
Units
ns, min ns, min ns, max ns, min ns, min MHz, max
DIN setup/hold, slave mode DIN setup/hold, master mode DOUT
CCLK
High time Low time Maximum Frequency Frequency Tolerance, master mode with respect to nominal
3.3V M0 M1 M2 DOUT VIRTEX-E MASTER SERIAL CCLK DIN PROGRAM DONE INIT 4.7 K N/C
N/C
M0 M1 M2 DIN CCLK
DOUT
XC1701L CLK DATA CEO CE RESET/OE (Low Reset Option Used)
VIRTEX-E, XC4000XL, SLAVE PROGRAM DONE
INIT
PROGRAM
XCVE_ds_013
Figure 13: Master/Slave Serial Mode Circuit Diagram
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DIN 1 TDCC CCLK 4 TCCH 3 TCCO DOUT (Output)
X5379_a
2 TCCD
5 TCCL
Figure 14: Slave-Serial Mode Programming Switching Characteristics
Master-Serial Mode
In master-serial mode, the CCLK output of the FPGA drives a Xilinx Serial PROM that feeds bit-serial data to the DIN input. The FPGA accepts this data on each rising CCLK edge. After the FPGA has been loaded, the data for the next device in a daisy-chain is presented on the DOUT pin after the rising CCLK edge. The interface is identical to slave-serial except that an internal oscillator is used to generate the configuration clock (CCLK). A wide range of frequencies can be selected for CCLK which always starts at a slow default frequency. Configuration bits then switch CCLK to a higher frequency for the remainder of the configuration. Switching to a lower frequency is prohibited. The CCLK frequency is set using the ConfigRate option in the bitstream generation software. The maximum CCLK frequency that can be selected is 60 MHz. When selecting a CCLK frequency, ensure that the serial PROM and any daisy-chained FPGAs are fast enough to support the clock rate. On power-up, the CCLK frequency is approximately 2.5 MHz. This frequency is used until the ConfigRate bits have been loaded when the frequency changes to the selected ConfigRate. Unless a different frequency is specified in the design, the default ConfigRate is 4 MHz. Figure 13 shows a full master/slave system. In this system, the left-most device operates in master-serial mode. The remaining devices operate in slave-serial mode. The SPROM
CCLK (Output) TCKDS 2 1 TDSCK Serial Data In
RESET pin is driven by INIT, and the CE input is driven by DONE. There is the potential for contention on the DONE pin, depending on the start-up sequence options chosen. The sequence of operations necessary to configure a Virtex-E FPGA serially appears in Figure 15.
Apply Power FPGA starts to clear configuration memory. Set PROGRAM = High FPGA makes a final clearing pass and releases INIT when finished.
Release INIT
If used to delay configuration
INIT?
Low
High
Load a Configuration Bit Once per bitstream, FPGA checks data using CRC and pulls INIT Low on error.
End of Bitstream? Yes
No
If no CRC errors found, FPGA enters start-up phase causing DONE to go High.
Configuration Completed
ds009_15_111799
Figure 15: Serial Configuration Flowchart Figure 16 shows the timing of master-serial configuration. Master-serial mode is selected by a <000> or <100> on the mode pins (M2, M1, M0). Table 10 shows the timing information for Figure 16
.
Serial DOUT (Output)
DS022_44_071201
Figure 16: Master-Serial Mode Programming Switching Characteristics
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At power-up, VCC must rise from 1.0 V to VCC min in less than 50 ms, otherwise delay configuration by pulling PROGRAM Low until VCC is valid.
Write
Write operations send packets of configuration data into the FPGA. The sequence of operations for a multi-cycle write operation is shown below. Note that a configuration packet can be split into many such sequences. The packet does not have to complete within one assertion of CS, illustrated in Figure 17. 1. Assert WRITE and CS Low. Note that when CS is asserted on successive CCLKs, WRITE must remain either asserted or de-asserted. Otherwise an abort is initiated, as described below. Drive data onto D[7:0]. Note that to avoid contention, the data source should not be enabled while CS is Low and WRITE is High. Similarly, while WRITE is High, no more that one CS should be asserted. At the rising edge of CCLK: If BUSY is Low, the data is accepted on this clock. If BUSY is High (from a previous write), the data is not accepted. Acceptance instead occurs on the first clock after BUSY goes Low, and the data must be held until this has happened. Repeat steps 2 and 3 until all the data has been sent. De-assert CS and WRITE.
SelectMAP Mode
The SelectMAP mode is the fastest configuration option. Byte-wide data is written into the FPGA with a BUSY flag controlling the flow of data. An external data source provides a byte stream, CCLK, a Chip Select (CS) signal and a Write signal (WRITE). If BUSY is asserted (High) by the FPGA, the data must be held until BUSY goes Low. Data can also be read using the SelectMAP mode. If WRITE is not asserted, configuration data is read out of the FPGA as part of a readback operation. After configuration, the pins of the SelectMAP port can be used as additional user I/O. Alternatively, the port can be retained to permit high-speed 8-bit readback. Retention of the SelectMAP port is selectable on a design-by-design basis when the bitstream is generated. If retention is selected, PROHIBIT constraints are required to prevent SelectMAP-port pins from being used as user I/O. Multiple Virtex-E FPGAs can be configured using the SelectMAP mode, and be made to start-up simultaneously. To configure multiple devices in this way, wire the individual CCLK, Data, WRITE, and BUSY pins of all the devices in parallel. The individual devices are loaded separately by asserting the CS pin of each device in turn and writing the appropriate data. See Table 11 for SelectMAP Write Timing Characteristics. Table 11: SelectMAP Write Timing Characteristics Description D0-7 Setup/Hold CS Setup/Hold WRITE Setup/Hold CCLK BUSY Propagation Delay Maximum Frequency Maximum Frequency with no handshake
2.
3.
4. 5.
Symbol 1/2 3/4 5/6 7 TSMDCC/TSMCCD TSMCSCC/TSMCCCS TSMCCW/TSMWCC TSMCKBY FCC FCCNH
Values 5.0 / 1.0 7.0 / 1.0 7.0 / 1.0 12.0 66 50
Units ns, min ns, min ns, min ns, max MHz, max MHz, max
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CCLK
CS
3
4
WRITE
5
6
1 DATA[0:7]
2
7 BUSY
No Write
Write
No Write
Write
DS022_45_071702
Figure 17: Write Operations A flowchart for the write operation appears in Figure 18. Note that if CCLK is slower than fCCNH, the FPGA never asserts BUSY, In this case, the above handshake is unnecessary, and data can simply be entered into the FPGA every CCLK cycle. Abort During a given assertion of CS, the user cannot switch from a write to a read, or vice-versa. This action causes the current packet command to be aborted. The device remains BUSY until the aborted operation has completed. Following an abort, data is assumed to be unaligned to word boundaries, and the FPGA requires a new synchronization word prior to accepting any new packets. To initiate an abort during a write operation, de-assert WRITE. At the rising edge of CCLK, an abort is initiated, as shown in Figure 19.
Apply Power FPGA starts to clear configuration memory. Set PROGRAM = High FPGA makes a final clearing pass and releases INIT when finished.
Release INIT
If used to delay configuration
INIT?
Low
High Set WRITE = Low
Enter Data Source Sequence A
Set CS = Low
On first FPGA
Apply Configuration Byte Once per bitstream, FPGA checks data using CRC and pulls INIT Low on error.
Busy?
High
Low No
End of Data? If no errors, first FPGAs enter start-up phase releasing DONE. Yes Set CS = High
On first FPGA
If no errors, later FPGAs enter start-up phase releasing DONE.
Repeat Sequence A
For any other FPGAs
Disable Data Source
Set WRITE = High When all DONE pins are released, DONE goes High and start-up sequences complete.
Configuration Completed ds009_18_111799
Figure 18: SelectMAP Flowchart for Write Operations
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VirtexTM-E 1.8 V Extended Memory Field Programmable Gate Arrays
CCLK
CS
WRITE
DATA[0:7]
BUSY
Abort
DS022_46_071702
Figure 19: SelectMAP Write Abort Waveforms
Boundary-Scan Mode
In the boundary-scan mode, no non-dedicated pins are required, configuration being done entirely through the IEEE 1149.1 Test Access Port. Configuration through the TAP uses the CFG_IN instruction. This instruction allows data input on TDI to be converted into data packets for the internal configuration bus. The following steps are required to configure the FPGA through the boundary-scan port (when using TCK as a start-up clock). 1. Load the CFG_IN instruction into the boundary-scan instruction register (IR) 2. Enter the Shift-DR (SDR) state 3. Shift a configuration bitstream into TDI 4. Return to Run-Test-Idle (RTI) 5. Load the JSTART instruction into IR 6. Enter the SDR state
7. 8.
Clock TCK through the startup sequence Return to RTI
Configuration and readback via the TAP is always available. The boundary-scan mode is selected by a <101> or <001> on the mode pins (M2, M1, M0).
Configuration Sequence
The configuration of Virtex-E devices is a three-phase process. First, the configuration memory is cleared. Next, configuration data is loaded into the memory, and finally, the logic is activated by a start-up process. Configuration is automatically initiated on power-up unless it is delayed by the user, as described below. The configuration process can also be initiated by asserting PROGRAM. The end of the memory-clearing phase is signalled by INIT going High, and the completion of the entire process is signalled by DONE going High. The power-up timing of configuration signals is shown in Figure 20.
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Vcc
TPOR
PROGRAM TPL
INIT TICCK CCLK OUTPUT or INPUT
M0, M1, M2 (Required)
VALI
ds022_020_071201
Figure 20: Power-Up Timing Configuration Signals The corresponding timing characteristics are listed in Table 12. Table 12: Power-up Timing Characteristics Symbol TPOR TPL TICCK TPROGRAM Value 2.0 100.0 0.5 CCLK (output) Delay Program Pulse Width 4.0 300 Units ms, max
s, max s, min s, max
Start-Up Sequence
The default Start-up sequence is that one CCLK cycle after DONE goes High, the global 3-state signal (GTS) is released. This permits device outputs to turn on as necessary. One CCLK cycle later, the Global Set/Reset (GSR) and Global Write Enable (GWE) signals are released. This permits the internal storage elements to begin changing state in response to the logic and the user clock. The relative timing of these events can be changed. In addition, the GTS, GSR, and GWE events can be made dependent on the DONE pins of multiple devices all going High, forcing the devices to start synchronously. The sequence can also be paused at any stage until lock has been achieved on any or all DLLs.
Description Power-on Reset1 Program Latency
ns, min
Notes: 1. TPOR delay is the initialization time required after VCCINT reaches the recommended operating voltage.
Delaying Configuration
INIT can be held Low using an open-drain driver. An open-drain is required since INIT is a bidirectional open-drain pin that is held Low by the FPGA while the configuration memory is being cleared. Extending the time that the pin is Low causes the configuration sequencer to wait. Thus, configuration is delayed by preventing entry into the phase where data is loaded.
Readback
The configuration data stored in the Virtex-E configuration memory can be readback for verification. Along with the configuration data it is possible to readback the contents all flip-flops/latches, LUT RAMs, and block RAMs. This capability is used for real-time debugging. For more detailed information, see application note XAPP138 "Virtex FPGA Series Configuration and Readback".
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Design Considerations
This section contains more detailed design information on the following features. * * * Delay-Locked Loop . . . see page 19 BlockRAM . . . see page 23 SelectI/O . . . see page 30 In order to guarantee the system clock establishes prior to the device "waking up," the DLL can delay the completion of the device configuration process until after the DLL achieves lock. By taking advantage of the DLL to remove on-chip clock delay, the designer can greatly simplify and improve system level design involving high-fanout, high-performance clocks.
Using DLLs
The Virtex-E FPGA series provides up to eight fully digital dedicated on-chip Delay-Locked Loop (DLL) circuits which provide zero propagation delay, low clock skew between output clock signals distributed throughout the device, and advanced clock domain control. These dedicated DLLs can be used to implement several circuits which improve and simplify system level design.
Library DLL Symbols
Figure 21 shows the simplified Xilinx library DLL macro symbol, BUFGDLL. This macro delivers a quick and efficient way to provide a system clock with zero propagation delay throughout the device. Figure 22 and Figure 23 show the two library DLL primitives. These symbols provide access to the complete set of DLL features when implementing more complex applications.
I O
Introduction
As FPGAs grow in size, quality on-chip clock distribution becomes increasingly important. Clock skew and clock delay impact device performance and the task of managing clock skew and clock delay with conventional clock trees becomes more difficult in large devices. The Virtex-E series of devices resolve this potential problem by providing up to eight fully digital dedicated on-chip DLL circuits which provide zero propagation delay and low clock skew between output clock signals distributed throughout the device. Each DLL can drive up to two global clock routing networks within the device. The global clock distribution network minimizes clock skews due to loading differences. By monitoring a sample of the DLL output clock, the DLL can compensate for the delay on the routing network, effectively eliminating the delay from the external input port to the individual clock loads within the device. In addition to providing zero delay with respect to a user source clock, the DLL can provide multiple phases of the source clock. The DLL can also act as a clock doubler or it can divide the user source clock by up to 16. Clock multiplication gives the designer a number of design alternatives. For instance, a 50 MHz source clock doubled by the DLL can drive an FPGA design operating at 100 MHz. This technique can simplify board design because the clock path on the board no longer distributes such a high-speed signal. A multiplied clock also provides designers the option of time-domain-multiplexing, using one circuit twice per clock cycle, consuming less area than two copies of the same circuit. Two DLLs in can be connected in series to increase the effective clock multiplication factor to four. The DLL can also act as a clock mirror. By driving the DLL output off-chip and then back in again, the DLL can be used to de-skew a board level clock between multiple devices.
0ns
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Figure 21: Simplified DLL Macro Symbol BUFGDLL
CLKDLL
CLKIN CLKFB CLK0 CLK90 CLK180 CLK270
CLK2X CLKDV RST LOCKED
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Figure 22: Standard DLL Symbol CLKDLL
CLKDLLHF
CLKIN CLKFB CLK0 CLK180
CLKDV RST LOCKED
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Figure 23: High Frequency DLL Symbol
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BUFGDLL Pin Descriptions
Use the BUFGDLL macro as the simplest way to provide zero propagation delay for a high-fanout on-chip clock from an external input. This macro uses the IBUFG, CLKDLL and BUFG primitives to implement the most basic DLL application as shown in Figure 24.
IBUFG I O CLKDLL
CLKIN CLKFB CLK0 CLK90 CLK180 CLK270
DLLs. This makes a total of eight usable input pins for DLLs in the Virtex-E family.
Feedback Clock Input -- CLKFB
The DLL requires a reference or feedback signal to provide the delay-compensated output. Connect only the CLK0 or CLK2X DLL outputs to the feedback clock input (CLKFB) pin to provide the necessary feedback to the DLL. The feedback clock input can also be provided through one of the following pins. IBUFG - Global Clock Input Pad IO_LVDS_DLL - the pin adjacent to IBUF If an IBUFG sources the CLKFB pin, the following special rules apply.
BUFG I O
CLK2X CLKDV RST LOCKED
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1. 2.
Figure 24: BUFGDLL Schematic This symbol does not provide access to the advanced clock domain controls or to the clock multiplication or clock division features of the DLL. This symbol also does not provide access to the RST, or LOCKED pins of the DLL. For access to these features, a designer must use the library DLL primitives described in the following sections.
An external input port must source the signal that drives the IBUFG I pin. The CLK2X output must feedback to the device if both the CLK0 and CLK2X outputs are driving off chip devices. That signal must directly drive only OBUFs and nothing else.
3.
Source Clock Input -- I
The I pin provides the user source clock, the clock signal on which the DLL operates, to the BUFGDLL. For the BUFGDLL macro the source clock frequency must fall in the low frequency range as specified in the data sheet. The BUFGDLL requires an external signal source clock. Therefore, only an external input port can source the signal that drives the BUFGDLL I pin.
These rules enable the software determine which DLL clock output sources the CLKFB pin.
Reset Input -- RST
When the reset pin RST activates the LOCKED signal deactivates within four source clock cycles. The RST pin, active High, must either connect to a dynamic signal or tied to ground. As the DLL delay taps reset to zero, glitches can occur on the DLL clock output pins. Activation of the RST pin can also severely affect the duty cycle of the clock output pins. Furthermore, the DLL output clocks no longer de-skew with respect to one another. For these reasons, rarely use the reset pin unless re-configuring the device or changing the input frequency.
Clock Output -- O
The clock output pin O represents a delay-compensated version of the source clock (I) signal. This signal, sourced by a global clock buffer BUFG symbol, takes advantage of the dedicated global clock routing resources of the device. The output clock has a 50-50 duty cycle unless you deactivate the duty cycle correction property.
2x Clock Output -- CLK2X
The output pin CLK2X provides a frequency-doubled clock with an automatic 50/50 duty-cycle correction. Until the CLKDLL has achieved lock, the CLK2X output appears as a 1x version of the input clock with a 25/75 duty cycle. This behavior allows the DLL to lock on the correct edge with respect to source clock. This pin is not available on the CLKDLLHF primitive.
CLKDLL Primitive Pin Descriptions
The library CLKDLL primitives provide access to the complete set of DLL features needed when implementing more complex applications with the DLL.
Source Clock Input -- CLKIN
The CLKIN pin provides the user source clock (the clock signal on which the DLL operates) to the DLL. The CLKIN frequency must fall in the ranges specified in the data sheet. A global clock buffer (BUFG) driven from another CLKDLL, one of the global clock input buffers (IBUFG), or an IO_LVDS_DLL pin on the same edge of the device (top or bottom) must source this clock signal. There are four IO_LVDS_DLL input pins that can be used as inputs to the
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Clock Divide Output -- CLKDV
The clock divide output pin CLKDV provides a lower frequency version of the source clock. The CLKDV_DIVIDE property controls CLKDV such that the source clock is divided by N where N is either 1.5, 2, 2.5, 3, 4, 5, 8, or 16. This feature provides automatic duty cycle correction such that the CLKDV output pin always has a 50/50 duty cycle, with the exception of noninteger divides in HF mode, where the duty cycle is 1/3 for N=1.5 and 2/5 for N=2.5.
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VirtexTM-E 1.8 V Extended Memory Field Programmable Gate Arrays The DLL clock outputs can drive an OBUF, a BUFG, or they can route directly to destination clock pins. The DLL clock outputs can only drive the BUFGs that reside on the same edge (top or bottom).
1x Clock Outputs -- CLK[0|90|180|270]
The 1x clock output pin CLK0 represents a delay-compensated version of the source clock (CLKIN) signal. The CLKDLL primitive provides three phase-shifted versions of the CLK0 signal while CLKDLLHF provides only the 180 phase-shifted version. The relationship between phase shift and the corresponding period shift appears in Table 13. Table 13: Relationship of Phase-Shifted Output Clock to Period Shift Period Shift (percent) 0% 25% 50% 75%
Locked Output -- LOCKED
To achieve lock, the DLL might need to sample several thousand clock cycles. After the DLL achieves lock, the LOCKED signal activates. The DLL timing parameter section of the data sheet provides estimates for locking times. To guarantee that the system clock is established prior to the device "waking up," the DLL can delay the completion of the device configuration process until after the DLL locks. The STARTUP_WAIT property activates this feature. Until the LOCKED signal activates, the DLL output clocks are not valid and can exhibit glitches, spikes, or other spurious movement. In particular the CLK2X output appears as a 1x clock with a 25/75 duty cycle.
Phase (degrees) 0 90 180 270
The timing diagrams in Figure 25 illustrate the DLL clock output characteristics.
0 90 180 270 0 90 180 270
DLL Properties
Properties provide access to some of the Virtex-E series DLL features, (for example, clock division and duty cycle correction).
t CLKIN CLK2X CLKDV_DIVIDE=2 CLKDV DUTY_CYCLE_CORRECTION=FALSE CLK0 CLK90 CLK180 CLK270 DUTY_CYCLE_CORRECTION=TRUE CLK0
Duty Cycle Correction Property
The 1x clock outputs, CLK0, CLK90, CLK180, and CLK270, use the duty-cycle corrected default, exhibiting a 50/50 duty cycle. The DUTY_CYCLE_CORRECTION property (by default TRUE) controls this feature. To deactivate the DLL duty-cycle correction for the 1x clock outputs, attach the DUTY_CYCLE_CORRECTION=FALSE property to the DLL symbol. When duty-cycle correction deactivates, the output clock has the same duty cycle as the source clock.
Clock Divide Property
The CLKDV_DIVIDE property specifies how the signal on the CLKDV pin is frequency divided with respect to the CLK0 pin. The values allowed for this property are 1.5, 2, 2.5, 3, 4, 5, 8, or 16; the default value is 2.
Startup Delay Property
CLK90 CLK180 CLK270
ds022_29_121099
This property, STARTUP_WAIT, takes on a value of TRUE or FALSE (the default value). When TRUE the device configuration DONE signal waits until the DLL locks before going to High.
Figure 25: DLL Output Characteristics The DLL provides duty cycle correction on all 1x clock outputs such that all 1x clock outputs by default have a 50/50 duty cycle. The DUTY_CYCLE_CORRECTION property (TRUE by default), controls this feature. In order to deactivate the DLL duty cycle correction, attach the DUTY_CYCLE_CORRECTION=FALSE property to the DLL symbol. When duty cycle correction deactivates, the output clock has the same duty cycle as the source clock.
Virtex-E DLL Location Constraints
As shown in Figure 26, there are four additional DLLs in the Virtex-E devices, for a total of eight per Virtex-E device. These DLLs are located in silicon, at the top and bottom of the two innermost block SelectRAM columns. The location constraint LOC, attached to the DLL symbol with the identifier DLL0S, DLL0P, DLL1S, DLL1P, DLL2S, DLL2P, DLL3S, or DLL3P, controls the DLL location. The LOC property uses the following form: LOC = DLL0P
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DLL-3S
DLL-3P
DLL-2P
DLL-2S
In a similar manner, a phase shift of the input clock is also possible. The phase shift propagates one to four clocks to the output after the original shift, with no disruption to the CLKDLL control.
B R A M
B R A M
B R A M
B R A M
Output Clocks
As mentioned earlier in the DLL pin descriptions, some restrictions apply regarding the connectivity of the output pins. The DLL clock outputs can drive an OBUF, a global clock buffer BUFG, or they can route directly to destination clock pins. The only BUFGs that the DLL clock outputs can drive are the two on the same edge of the device (top or bottom). In addition, the CLK2X output of the secondary DLL can connect directly to the CLKIN of the primary DLL in the same quadrant. Do not use the DLL output clock signals until after activation of the LOCKED signal. Prior to the activation of the LOCKED signal, the DLL output clocks are not valid and can exhibit glitches, spikes, or other spurious movement.
DLL-1S
DLL-1P
DLL-0P
DLL-0S
Bottom Right Half Edge
x132_14_100799
Figure 26: Virtex Series DLLs
Design Factors
Use the following design considerations to avoid pitfalls and improve success designing with Xilinx devices.
Input Clock
The output clock signal of a DLL, essentially a delayed version of the input clock signal, reflects any instability on the input clock in the output waveform. For this reason the quality of the DLL input clock relates directly to the quality of the output clock waveforms generated by the DLL. The DLL input clock requirements are specified in the data sheet. In most systems a crystal oscillator generates the system clock. The DLL can be used with any commercially available quartz crystal oscillator. For example, most crystal oscillators produce an output waveform with a frequency tolerance of 100 PPM, meaning 0.01 percent change in the clock period. The DLL operates reliably on an input waveform with a frequency drift of up to 1 ns -- orders of magnitude in excess of that needed to support any crystal oscillator in the industry. However, the cycle-to-cycle jitter must be kept to less than 300 ps in the low frequencies and 150 ps for the high frequencies.
Useful Application Examples
The Virtex-E DLL can be used in a variety of creative and useful applications. The following examples show some of the more common applications. The Verilog and VHDL example files are available at:
ftp://ftp.xilinx.com/pub/applications/xapp/xapp132.zip
Standard Usage
The circuit shown in Figure 27 resembles the BUFGDLL macro implemented to provide access to the RST and LOCKED pins of the CLKDLL.
IBUFG CLKIN CLKFB
CLKDLL
CLK0 CLK90 CLK180 CLK270
BUFG
Input Clock Changes
Changing the period of the input clock beyond the maximum drift amount requires a manual reset of the CLKDLL. Failure to reset the DLL produces an unreliable lock signal and output clock. It is possible to stop the input clock with little impact to the DLL. Stopping the clock should be limited to less than 100 s to keep device cooling to a minimum. The clock should be stopped during a Low phase, and when restored the full High period should be seen. During this time LOCKED stays High and remains High when the clock is restored. When the clock is stopped, one to four more clocks are still observed as the delay line is flushed. When the clock is restarted, the output clocks are not observed for one to four clocks as the delay line is filled. The most common case is two or three clocks.
IBUF RST
CLK2X CLKDV OBUF LOCKED
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Figure 27: Standard DLL Implementation
Board Level De-Skew of Multiple Non-Virtex-E Devices
The circuit shown in Figure 28 can be used to de-skew a system clock between a Virtex-E chip and other non-Virtex-E chips on the same board. This application is commonly used when the Virtex-E device is used in conjunction with other standard products such as SRAM or DRAM devices. While designing the board level route, ensure that the return net delay to the source equals the delay to the other chips involved.
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VirtexTM-E 1.8 V Extended Memory Field Programmable Gate Arrays Because any single DLL can access only two BUFGs at most, any additional output clock signals must be routed from the DLL in this example on the high speed backbone routing. The dll_2x files in the xapp132.zip file show the VHDL and Verilog implementation of this circuit.
Virtex-E Device IBUFG CLKIN CLKFB IBUFG CLKDLL CLK0 CLK90 CLK180 CLK270 OBUF
CLK2X CLKDV RST LOCKED
Virtex-E 4x Clock
Two DLLs located in the same half-edge (top-left, top-right, bottom-right, bottom-left) can be connected together, without using a BUFG between the CLKDLLs, to generate a 4x clock as shown in Figure 30. Virtex-E devices, like the Virtex devices, have four clock networks that are available for internal de-skewing of the clock. Each of the eight DLLs have access to two of the four clock networks. Although all the DLLs can be used for internal de-skewing, the presence of two GCLKBUFs on the top and two on the bottom indicate that only two of the four DLLs on the top (and two of the four DLLs on the bottom) can be used for this purpose.
IBUFG
CLKDLL CLKIN CLKFB CLK0 CLK90 CLK180 CLK270
BUFG
CLK2X CLKDV RST LOCKED
Non-Virtex-E Chip Non-Virtex-E Chip
CLKDLL-S CLKIN CLKFB CLK0 CLK90 CLK180 CLK270 CLK2X
Other Non_Virtex-E Chips
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Figure 28: DLL De-skew of Board Level Clock Board-level de-skew is not required for low-fanout clock networks. It is recommended for systems that have fanout limitations on the clock network, or if the clock distribution chip cannot handle the load. Do not use the DLL output clock signals until after activation of the LOCKED signal. Prior to the activation of the LOCKED signal, the DLL output clocks are not valid and can exhibit glitches, spikes, or other spurious movement. The dll_mirror_1 files in the xapp132.zip file show the VHDL and Verilog implementation of this circuit.
RST
CLKDV LOCKED
INV
CLKDLL-P CLKIN CLKFB CLK0 CLK90 CLK180 CLK270
BUFG
CLK2X CLKDV RST LOCKED
OBUF
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De-Skew of Clock and Its 2x Multiple
The circuit shown in Figure 29 implements a 2x clock multiplier and also uses the CLK0 clock output with zero ns skew between registers on the same chip. A clock divider circuit could alternatively be implemented using similar connections.
IBUFG CLKIN CLKFB
Figure 30: DLL Generation of 4x Clock in Virtex-E Devices The dll_4xe files in the xapp 32.zip file show the DLL implementation in Verilog for Virtex-E devices. These files can be found at:
ftp://ftp.xilinx.com/pub/applications/xapp/xapp132.zip
CLKDLL
CLK0 CLK90 CLK180 CLK270
BUFG
Using Block SelectRAM+ Features
BUFG OBUF
CLK2X IBUF RST CLKDV LOCKED
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Figure 29: DLL De-skew of Clock and 2x Multiple
The Virtex FPGA Series provides dedicated blocks of on-chip, true dual-read/write port synchronous RAM, with 4096 memory cells. Each port of the block SelectRAM+ memory can be independently configured as a read/write port, a read port, a write port, and can be configured to a specific data width. block SelectRAM+ memory offers new capabilities, allowing FPGA designers to simplify designs.
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Operating Modes
Virtex-E block SelectRAM+ memory supports two operating modes. * * Read Through Write Back
RAMB4_S#_S#
WEA ENA RSTA CLKA ADDRA[#:0] DIA[#:0]
DOA[#:0]
Read Through (one clock edge)
The read address is registered on the read port clock edge and data appears on the output after the RAM access time. Some memories might place the latch/register at the outputs, depending on the desire to have a faster clock-to-out versus set-up time. This is generally considered to be an inferior solution, since it changes the read operation to an asynchronous function with the possibility of missing an address/control line transition during the generation of the read pulse clock.
WEB ENB RSTB CLKB ADDRB[#:0] DIB[#:0] DOB[#:0]
ds022_032_121399
Figure 31: Dual-Port Block SelectRAM+ Memory
Write Back (one clock edge)
The write address is registered on the write port clock edge and the data input is written to the memory and mirrored on the output.
RAMB4_S#
WE EN RST CLK ADDR[#:0] DI[#:0]
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DO[#:0]
Block SelectRAM+ Characteristics
1. All inputs are registered with the port clock and have a set-up to clock timing specification. 2. All outputs have a read through or write back function depending on the state of the port WE pin. The outputs relative to the port clock are available after the clock-to-out timing specification. 3. The block SelectRAM elements are true SRAM memories and do not have a combinatorial path from the address to the output. The LUT SelectRAM+ cells in the CLBs are still available with this function. 4. The ports are completely independent from each other (i.e., clocking, control, address, read/write function, and data width) without arbitration. 5. A write operation requires only one clock edge. 6. A read operation requires only one clock edge. The output ports are latched with a self-timed circuit to guarantee a glitch-free read. The state of the output port does not change until the port executes another read or write operation.
Figure 32: Single-Port Block SelectRAM+ Memory Table 14: Available Library Primitives Port A Width 1 Port B Width N/A 1 2 4 8 16 2 N/A 2 4 8 16 4 N/A 4 8 16 8 N/A 8 16 16 N/A 16
Primitive RAMB4_S1 RAMB4_S1_S1 RAMB4_S1_S2 RAMB4_S1_S4 RAMB4_S1_S8 RAMB4_S1_S16 RAMB4_S2 RAMB4_S2_S2 RAMB4_S2_S4 RAMB4_S2_S8 RAMB4_S2_S16 RAMB4_S4 RAMB4_S4_S4 RAMB4_S4_S8 RAMB4_S4_S16 RAMB4_S8 RAMB4_S8_S8 RAMB4_S8_S16 RAMB4_S16 RAMB4_S16_S16
Library Primitives
Figure 31 and Figure 32 show the two generic library block SelectRAM+ primitives. Table 14 describes all of the available primitives for synthesis and simulation.
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Port Signals
Each block SelectRAM+ port operates independently of the others while accessing the same set of 4096 memory cells. Table 15 describes the depth and width aspect ratios for the block SelectRAM+ memory. Table 15: Width 1 2 4 8 16 Block SelectRAM+ Port Aspect Ratios Depth 4096 2048 1024 512 256 ADDR Bus ADDR<11:0> ADDR<10:0> ADDR<9:0> ADDR<8:0> ADDR<7:0> Data Bus DATA<0> DATA<1:0> DATA<3:0> DATA<7:0> DATA<15:0>
Data Output Bus--DO[A|B]<#:0>
The data out bus reflects the contents of the memory cells referenced by the address bus at the last active clock edge. During a write operation, the data out bus reflects the data in bus. The width of this bus equals the width of the port. The allowed widths appear in Table 15.
Inverting Control Pins
The four control pins (CLK, EN, WE and RST) for each port have independent inversion control as a configuration option.
Address Mapping
Each port accesses the same set of 4096 memory cells using an addressing scheme dependent on the width of the port. The physical RAM location addressed for a particular width are described in the following formula (of interest only when the two ports use different aspect ratios). Start = ((ADDRport +1) * Widthport) -1 End = ADDRport * Widthport Table 16 shows low order address mapping for each port width. Table 16: Port Width
1 2 4 8 16 4095... 2047... 1023... 511... 255...
Clock--CLK[A|B]
Each port is fully synchronous with independent clock pins. All port input pins have setup time referenced to the port CLK pin. The data output bus has a clock-to-out time referenced to the CLK pin.
Enable--EN[A|B]
The enable pin affects the read, write and reset functionality of the port. Ports with an inactive enable pin keep the output pins in the previous state and do not write data to the memory cells. Port Address Mapping Port Addresses
1111110000000000 5432109876543210 07 03 01 00 06 05 02 04 03 01 00 02 01 00 00
Write Enable--WE[A|B]
Activating the write enable pin allows the port to write to the memory cells. When active, the contents of the data input bus are written to the RAM at the address pointed to by the address bus, and the new data also reflects on the data out bus. When inactive, a read operation occurs and the contents of the memory cells referenced by the address bus reflect on the data out bus.
Creating Larger RAM Structures
The block SelectRAM+ columns have specialized routing to allow cascading blocks together with minimal routing delays. This achieves wider or deeper RAM structures with a smaller timing penalty than when using normal routing channels.
Reset--RST[A|B]
The reset pin forces the data output bus latches to zero synchronously. This does not affect the memory cells of the RAM and does not disturb a write operation on the other port.
Address Bus--ADDR[A|B]<#:0>
The address bus selects the memory cells for read or write. The width of the port determines the required width of this bus as shown in Table 15.
Location Constraints
Block SelectRAM+ instances can have LOC properties attached to them to constrain the placement. The block SelectRAM+ placement locations are separate from the CLB location naming convention, allowing the LOC properties to transfer easily from array to array. The LOC properties use the following form. LOC = RAMB4_R#C# RAMB4_R0C0 is the upper left RAMB4 location on the device.
Data In Bus--DI[A|B]<#:0>
The data in bus provides the new data value to be written into the RAM. This bus and the port have the same width, as shown in Table 15.
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Conflict Resolution
The block SelectRAM+ memory is a true dual-read/write port RAM that allows simultaneous access of the same memory cell from both ports. When one port writes to a given memory cell, the other port must not address that memory cell (for a write or a read) within the clock-to-clock setup window. The following lists specifics of port and memory cell write conflict resolution. * If both ports write to the same memory cell simultaneously, violating the clock-to-clock setup requirement, consider the data stored as invalid. If one port attempts a read of the same memory cell the other simultaneously writes, violating the clock-to-clock setup requirement, the following occurs. The write succeeds The data out on the writing port accurately reflects the data written. The data out on the reading port is invalid. and the WE pin is Low indicating a read operation. The DO bus contains the contents of the memory location 0x7E as indicated by the ADDR bus. At the fourth rising edge of the CLK pin, the ADDR, DI, EN, WR, and RST pins are sampled again. The EN pin is Low indicating that the block SelectRAM+ memory is now disabled. The DO bus retains the last value.
Dual Port Timing
Figure 34 shows a timing diagram for a true dual-port read/write block SelectRAM+ memory. The clock on port A has a longer period than the clock on Port B. The timing parameter TBCCS, (clock-to-clock set-up) is shown on this diagram. The parameter, TBCCS is violated once in the diagram. All other timing parameters are identical to the single port version shown in Figure 33. TBCCS is only of importance when the address of both ports are the same and at least one port is performing a write operation. When the clock-to-clock set-up parameter is violated for a WRITE-WRITE condition, the contents of the memory at that location are invalid. When the clock-to-clock set-up parameter is violated for a WRITE-READ condition, the contents of the memory are correct, but the read port has invalid data. At the first rising edge of CLKA, memory location 0x00 is to be written with the value 0xAAAA and is mirrored on the DOA bus. The last operation of Port B was a read to the same memory location 0x00. The DOB bus of Port B does not change with the new value on Port A, and retains the last read value. A short time later, Port B executes another read to memory location 0x00, and the DOB bus now reflects the new memory value written by Port A. At the second rising edge of CLKA, memory location 0x7E is written with the value 0x9999 and is mirrored on the DOA bus. Port B then executes a read operation to the same memory location without violating the TBCCS parameter and the DOB reflects the new memory values written by Port A.
*
Conflicts do not cause any physical damage.
Single Port Timing
Figure 33 shows a timing diagram for a single port of a block SelectRAM+ memory. The block SelectRAM+ AC switching characteristics are specified in the data sheet. The block SelectRAM+ memory is initially disabled. At the first rising edge of the CLK pin, the ADDR, DI, EN, WE, and RST pins are sampled. The EN pin is High and the WE pin is Low indicating a read operation. The DO bus contains the contents of the memory location, 0x00, as indicated by the ADDR bus. At the second rising edge of the CLK pin, the ADDR, DI, EN, WR, and RST pins are sampled again. The EN and WE pins are High indicating a write operation. The DO bus mirrors the DI bus. The DI bus is written to the memory location 0x0F. At the third rising edge of the CLK pin, the ADDR, DI, EN, WR, and RST pins are sampled again. The EN pin is High
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VirtexTM-E 1.8 V Extended Memory Field Programmable Gate Arrays
TBPWH
TBPWL
CLK
TBACK
ADDR DIN DOUT
00 TBDCK DDDD TBCKO MEM (00) TBECK
0F CCCC CCCC
7E BBBB MEM (7E)
8F 2222
EN RST
TBWCK
WE
DISABLED READ WRITE READ DISABLED
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Figure 33: Timing Diagram for Single Port Block SelectRAM+ Memory
TBCCS VIOLATION
CLK_A ADDR_A PORT A EN_A WE_A DI_A DO_A
AAAA 9999 AAAA 0000 1111 00 7E 0F 0F 7E
TBCCS TBCCS
AAAA
9999
AAAA
UNKNOWN
2222
CLK_B ADDR_B EN_B WE_B DI_B DO_B
1111 1111 1111 BBBB 1111 2222 FFFF 00 00 7E 0F 0F 7E 1A
PORT B
MEM (00)
AAAA
9999
BBBB
UNKNOWN
2222
FFFF
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Figure 34: Timing Diagram for a True Dual-port Read/Write Block SelectRAM+ Memory At the third rising edge of CLKA, the TBCCS parameter is violated with two writes to memory location 0x0F. The DOA and DOB busses reflect the contents of the DIA and DIB busses, but the stored value at 0x0F is invalid. At the fourth rising edge of CLKA, a read operation is performed at memory location 0x0F and invalid data is present on the DOA bus. Port B also executes a read operation to memory location 0x0F and also reads invalid data. At the fifth rising edge of CLKA a read operation is performed that does not violate the TBCCS parameter to the previous write of 0x7E by Port B. THe DOA bus reflects the recently written value by Port B.
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Initialization
The block SelectRAM+ memory can initialize during the device configuration sequence. The 16 initialization properties of 64 hex values each (a total of 4096 bits) set the initialization of each RAM. These properties appear in Table 17. Any initialization properties not explicitly set configure as zeros. Partial initialization strings pad with zeros. Initialization strings greater than 64 hex values generate an error. The RAMs can be simulated with the initialization values using generics in VHDL simulators and parameters in Verilog simulators.
Design Examples
Creating a 32-bit Single-Port RAM
The true dual-read/write port functionality of the block SelectRAM+ memory allows a single port, 128 deep by 32-bit wide RAM to be created using a single block SelectRAM+ cell as shown inTable 35. Interleaving the memory space, setting the LSB of the address bus of Port A to 1 (VCC), and the LSB of the address bus of Port B to 0 (GND), allows a 32-bit wide single port RAM to be created.
RAMB4_S16_S16
WE EN RST CLK ADDR[6:0], V CC DI[31:16] WEA ENA RSTA CLKA ADDRA[7:0] DIA[15:0]
Initialization in VHDL and Synopsys
The block SelectRAM+ structures can be initialized in VHDL for both simulation and synthesis for inclusion in the EDIF output file. The simulation of the VHDL code uses a generic to pass the initialization. Synopsys FPGA compiler does not presently support generics. The initialization values instead attach as attributes to the RAM by a built-in Synopsys dc_script. The translate_off statement stops synthesis translation of the generic statements. The following code illustrates a module that employs these techniques. Table 17: RAM Initialization Properties Property INIT_00 INIT_01 INIT_02 INIT_03 INIT_04 INIT_05 INIT_06 INIT_07 INIT_08 INIT_09 INIT_0a INIT_0b INIT_0c INIT_0d INIT_0e INIT_0f Memory Cells 255 to 0 511 to 256 767 to 512 1023 to 768 1279 to 1024 1535 to 1280 1791 to 2047 2047 to 1792 2303 to 2048 2559 to 2304 2815 to 2560 3071 to 2816 3327 to 3072 3583 to 3328 3839 to 3584 4095 to 3840
DOA[15:0]
DO[31:16]
WE EN RST CLK ADDR[6:0], GND DI[15:0]
WEB ENB RSTB CLKB ADDRB[7:0] DIB[15:0]
DOB[15:0]
DO[15:0]
ds022_036_121399
Figure 35: Single Port 128 x 32 RAM
Creating Two Single-Port RAMs
The true dual-read/write port functionality of the block SelectRAM+ memory allows a single RAM to be split into two single port memories of 2K bits each as shown in Figure 36.
RAMB4_S4_S16
WE1 EN1 RST1 CLK1 V CC , ADDR1[8:0] DI1[3:0] WEA ENA RSTA CLKA ADDRA[9:0] DIA[3:0]
DOA[3:0]
DO1[3:0]
WE2 EN2 RST2 CLK2 GND, ADDR2[6:0] DI2[15:0]
WEB ENB RSTB CLKB ADDRB[7:0] DIB[15:0]
DOB[15:0]
DO2[15:0]
ds022_037_121399
Figure 36: 512 x 4 RAM and 128 x 16 RAM In this example, a 512K x 4 RAM (Port A) and a 128 x 16 RAM (Port B) are created out of a single block SelectRAM+. The address space for the RAM is split by fixing the MSB of Port A to 1 (VCC) for the upper 2K bits and the MSB of Port B to 0 (GND) for the lower 2K bits.
Initialization in Verilog and Synopsys
The block SelectRAM+ structures can be initialized in Verilog for both simulation and synthesis for inclusion in the EDIF output file. The simulation of the Verilog code uses a defparam to pass the initialization. The Synopsys FPGA compiler does not presently support defparam. The initialization values instead attach as attributes to the RAM by a built-in Synopsys dc_script. The translate_off statement stops synthesis translation of the defparam statements. The following code illustrates a module that employs these techniques.
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Block Memory Generation
The CoreGen program generates memory structures using the block SelectRAM+ features. This program outputs VHDL or Verilog simulation code templates and an EDIF file for inclusion in a design.
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VHDL Initialization Example
library IEEE; use IEEE.std_logic_1164.all; entity MYMEM is port (CLK, WE:in std_logic; ADDR: in std_logic_vector(8 downto 0); DIN: in std_logic_vector(7 downto 0); DOUT: out std_logic_vector(7 downto 0)); end MYMEM; architecture BEHAVE of MYMEM is signal logic0, logic1: std_logic; component RAMB4_S8 --synopsys translate_off generic( INIT_00,INIT_01, INIT_02, INIT_03, INIT_04, INIT_05, INIT_06, INIT_07, INIT_08, INIT_09, INIT_0a, INIT_0b, INIT_0c, INIT_0d, INIT_0e, INIT_0f : BIT_VECTOR(255 downto 0) := X"0000000000000000000000000000000000000000000000000000000000000000"); --synopsys translate_on port (WE, EN, RST, CLK: in STD_LOGIC; ADDR: in STD_LOGIC_VECTOR(8 downto 0); DI: in STD_LOGIC_VECTOR(7 downto 0); DO: out STD_LOGIC_VECTOR(7 downto 0)); end component; --synopsys dc_script_begin --set_attribute ram0 INIT_00 "0123456789ABCDEF0123456789ABCDEF0123456789ABCDEF0123456789ABCDEF" -type string --set_attribute ram0 INIT_01 "FEDCBA9876543210FEDCBA9876543210FEDCBA9876543210FEDCBA9876543210" -type string --synopsys dc_script_end begin logic0 <='0'; logic1 <='1'; ram0: RAMB4_S8 --synopsys translate_off generic map ( INIT_00 => X"0123456789ABCDEF0123456789ABCDEF0123456789ABCDEF0123456789ABCDEF", INIT_01 => X"FEDCBA9876543210FEDCBA9876543210FEDCBA9876543210FEDCBA9876543210") --synopsys translate_on port map (WE=>WE, EN=>logic1, RST=>logic0, CLK=>CLK,ADDR=>ADDR, DI=>DIN, DO=>DOUT); end BEHAVE;
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Verilog Initialization Example
module MYMEM (CLK, WE, ADDR, DIN, DOUT); input CLK, WE; input [8:0] ADDR; input [7:0] DIN; output [7:0] DOUT; wire logic0, logic1; //synopsys dc_script_begin //set_attribute ram0 INIT_00 "0123456789ABCDEF0123456789ABCDEF0123456789ABCDEF0123456789ABCDEF" -type string //set_attribute ram0 INIT_01 "FEDCBA9876543210FEDCBA9876543210FEDCBA9876543210FEDCBA9876543210" -type string //synopsys dc_script_end assign logic0 = 1'b0; assign logic1 = 1'b1; RAMB4_S8 ram0 (.WE(WE), .EN(logic1), .RST(logic0), .CLK(CLK), .ADDR(ADDR), .DI(DIN), .DO(DOUT)); //synopsys translate_off defparam ram0.INIT_00 = 256h'0123456789ABCDEF0123456789ABCDEF0123456789ABCDEF0123456789ABCDEF; defparam ram0.INIT_01 = 256h'FEDCBA9876543210FEDCBA9876543210FEDCBA9876543210FEDCBA9876543210; //synopsys translate_on endmodule
Using SelectI/O
The Virtex-E FPGA series includes a highly configurable, high-performance I/O resource, called SelectI/OTM to provide support for a wide variety of I/O standards. The SelectI/O resource is a robust set of features including programmable control of output drive strength, slew rate, and input delay and hold time. Taking advantage of the flexibility and SelectI/O features and the design considerations described in this document can improve and simplify system level design. with the high performance previously available only with ASICs and custom ICs. Each SelectI/O block can support up to 20 I/O standards. Supporting such a variety of I/O standards allows the support of a wide variety of applications, from general purpose standard applications to high-speed low-voltage memory busses. SelectI/O blocks also provide selectable output drive strengths and programmable slew rates for the LVTTL output buffers, as well as an optional, programmable weak pull-up, weak pull-down, or weak "keeper" circuit ideal for use in external bussing applications. Each input/output block (IOB) includes three registers, one each for the input, output, and 3-state signals within the IOB. These registers are optionally configurable as either a D-type flip-flop or as a level sensitive latch. The input buffer has an optional delay element used to guarantee a zero hold time requirement for input signals registered within the IOB. The Virtex-E SelectI/O features also provide dedicated resources for input reference voltage (VREF) and output source voltage (VCCO), along with a convenient banking system that simplifies board design. By taking advantage of the built-in features and wide variety of I/O standards supported by the SelectI/O features, system-level design and board design can be greatly simplified and improved.
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Introduction
As FPGAs continue to grow in size and capacity, the larger and more complex systems designed for them demand an increased variety of I/O standards. Furthermore, as system clock speeds continue to increase, the need for high performance I/O becomes more important. While chip-to-chip delays have an increasingly substantial impact on overall system speed, the task of achieving the desired system performance becomes more difficult with the proliferation of low-voltage I/O standards. SelectI/O, the revolutionary input/output resource of Virtex-E devices, has resolved this potential problem by providing a highly configurable, high-performance alternative to the I/O resources of more conventional programmable devices. The Virtex-E SelectI/O features combine the flexibility and time-to-market advantages of programmable logic
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Fundamentals
Modern bus applications, pioneered by the largest and most influential companies in the digital electronics industry, are commonly introduced with a new I/O standard tailored specifically to the needs of that application. The bus I/O standards provide specifications to other vendors who create products designed to interface with these applications. Each standard often has its own specifications for current, voltage, I/O buffering, and termination techniques. The ability to provide the flexibility and time-to-market advantages of programmable logic is increasingly dependent on the capability of the programmable logic device to support an ever increasing variety of I/O standards The SelectI/O resources feature highly configurable input and output buffers which provide support for a wide variety of I/O standards. As shown in Table 18, each buffer type can support a variety of voltage requirements. Table 18: I/O Standard LVTTL LVCMOS2 LVCMOS18 SSTL3 I & II SSTL2 I & II GTL GTL+ HSTL I HSTL III & IV CTT AGP-2X PCI33_3 PCI66_3 BLVDS & LVDS LVPECL Virtex-E Supported I/O Standards Output VCCO 3.3 2.5 1.8 3.3 2.5 N/A N/A 1.5 1.5 3.3 3.3 3.3 3.3 2.5 3.3 Input VCCO 3.3 2.5 1.8 N/A N/A N/A N/A N/A N/A N/A N/A 3.3 3.3 N/A N/A Input VREF N/A N/A N/A 1.50 1.25 0.80 1.0 0.75 0.90 1.50 1.32 N/A N/A N/A N/A Board Termination Voltage (VTT) N/A N/A N/A 1.50 1.25 1.20 1.50 0.75 1.50 1.50 N/A N/A N/A N/A N/A
Overview of Supported I/O Standards
This section provides a brief overview of the I/O standards supported by all Virtex-E devices. While most I/O standards specify a range of allowed voltages, this document records typical voltage values only. Detailed information on each specification can be found on the Electronic Industry Alliance Jedec website at: http://www.jedec.org
LVTTL -- Low-Voltage TTL
The Low-Voltage TTL, or LVTTL standard is a general purpose EIA/JESDSA standard for 3.3 V applications that uses an LVTTL input buffer and a Push-Pull output buffer. This standard requires a 3.3 V output source voltage (VCCO), but does not require the use of a reference voltage (VREF) or a termination voltage (VTT).
LVCMOS2 -- Low-Voltage CMOS for 2.5 Volts
The Low-Voltage CMOS for 2.5 Volts or lower, or LVCMOS2 standard is an extension of the LVCMOS standard (JESD 8.-5) used for general purpose 2.5 V applications. This standard requires a 2.5 V output source voltage (VCCO), but does not require the use of a reference voltage (VREF) or a board termination voltage (VTT).
LVCMOS18 -- 1.8 V Low Voltage CMOS
This standard is an extension of the LVCMOS standard. It is used in general purpose 1.8 V applications. The use of a reference voltage (VREF) or a board termination voltage (VTT) is not required.
PCI -- Peripheral Component Interface
The Peripheral Component Interface, or PCI standard specifies support for both 33 MHz and 66 MHz PCI bus applications. It uses a LVTTL input buffer and a Push-Pull output buffer. This standard does not require the use of a reference voltage (VREF) or a board termination voltage (VTT), however, it does require a 3.3 V output source voltage (VCCO).
GTL -- Gunning Transceiver Logic Terminated
The Gunning Transceiver Logic, or GTL standard is a high-speed bus standard (JESD8.3) invented by Xerox. Xilinx has implemented the terminated variation for this standard. This standard requires a differential amplifier input buffer and a Open Drain output buffer.
GTL+ -- Gunning Transceiver Logic Plus
The Gunning Transceiver Logic Plus, or GTL+ standard is a high-speed bus standard (JESD8.3) first used by the Pentium Pro processor.
HSTL -- High-Speed Transceiver Logic
The High-Speed Transceiver Logic, or HSTL standard is a general purpose high-speed, 1.5 V bus standard sponsored by IBM (EIA/JESD 8-6). This standard has four variations or classes. SelectI/O devices support Class I, III, and IV. This
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Library Symbols
The Xilinx library includes an extensive list of symbols designed to provide support for the variety of SelectI/O features. Most of these symbols represent variations of the five generic SelectI/O symbols. * * * * * IBUF (input buffer) IBUFG (global clock input buffer) OBUF (output buffer) OBUFT (3-state output buffer) IOBUF (input/output buffer)
SSTL3 -- Stub Series Terminated Logic for 3.3V
The Stub Series Terminated Logic for 3.3 V, or SSTL3 standard is a general purpose 3.3 V memory bus standard also sponsored by Hitachi and IBM (JESD8-8). This standard has two classes, I and II. SelectI/O devices support both classes for the SSTL3 standard. This standard requires a Differential Amplifier input buffer and an Push-Pull output buffer.
SSTL2 -- Stub Series Terminated Logic for 2.5V
The Stub Series Terminated Logic for 2.5 V, or SSTL2 standard is a general purpose 2.5 V memory bus standard sponsored by Hitachi and IBM (JESD8-9). This standard has two classes, I and II. SelectI/O devices support both classes for the SSTL2 standard. This standard requires a Differential Amplifier input buffer and an Push-Pull output buffer.
IBUF
Signals used as inputs to the Virtex-E device must source an input buffer (IBUF) via an external input port. The generic Virtex-E IBUF symbol appears in Figure 37. The extension to the base name defines which I/O standard the IBUF uses. The assumed standard is LVTTL when the generic IBUF has no specified extension.
CTT -- Center Tap Terminated
The Center Tap Terminated, or CTT standard is a 3.3 V memory bus standard sponsored by Fujitsu (JESD8-4). This standard requires a Differential Amplifier input buffer and a Push-Pull output buffer.
IBUF I O
x133_01_111699
AGP-2X -- Advanced Graphics Port
The Intel AGP standard is a 3.3 V Advanced Graphics Port-2X bus standard used with the Pentium II processor for graphics applications. This standard requires a Push-Pull output buffer and a Differential Amplifier input buffer.
Figure 37: Input Buffer (IBUF) Symbols The following list details the variations of the IBUF symbol: * * * * * * * * * * * * * * * * * * IBUF IBUF_LVCMOS2 IBUF_PCI33_3 IBUF_PCI66_3 IBUF_GTL IBUF_GTLP IBUF_HSTL_I IBUF_HSTL_III IBUF_HSTL_IV IBUF_SSTL3_I IBUF_SSTL3_II IBUF_SSTL2_I IBUF_SSTL2_II IBUF_CTT IBUF_AGP IBUF_LVCMOS18 IBUF_LVDS IBUF_LVPECL
LVDS -- Low Voltage Differential Signal
LVDS is a differential I/O standard. It requires that one data bit is carried through two signal lines. As with all differential signaling standards, LVDS has an inherent noise immunity over single-ended I/O standards. The voltage swing between two signal lines is approximately 350 mV. The use of a reference voltage (VREF) or a board termination voltage (VTT) is not required. LVDS requires the use of two pins per input or output. LVDS requires external resistor termination.
BLVDS -- Bus LVDS
This standard allows for bidirectional LVDS communication between two or more devices. The external resistor termination is different than the one for standard LVDS.
LVPECL -- Low Voltage Positive Emitter Coupled Logic
LVPECL is another differential I/O standard. It requires two signal lines for transmitting one data bit. This standard specifies two pins per input or output. The voltage swing between these two signal lines is approximately 850 mV. The use of a reference voltage (VREF) or a board termination voltage (VTT) is not required. The LVPECL standard requires external resistor termination.
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When the IBUF symbol supports an I/O standard that requires a VREF, the IBUF automatically configures as a differential amplifier input buffer. The VREF voltage must be supplied on the VREF pins. In the case of LVDS, LVPECL, and BLVDS, VREF is not required.
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VirtexTM-E 1.8 V Extended Memory Field Programmable Gate Arrays CLKDLLHF, or a BUFG symbol. The generic Virtex-E IBUFG symbol appears in Figure 39.
The voltage reference signal is "banked" within the Virtex-E device on a half-edge basis such that for all packages there are eight independent VREF banks internally. See Figure 38 for a representation of the Virtex-E I/O banks. Within each bank approximately one of every six I/O pins is automatically configured as a VREF input. After placing a differential amplifier input signal within a given VREF bank, the same external source must drive all I/O pins configured as a VREF input. IBUF placement restrictions require that any differential amplifier input signals within a bank be of the same standard. How to specify a specific location for the IBUF via the LOC property is described below. Table 19 summarizes the Virtex-E input standards compatibility requirements. An optional delay element is associated with each IBUF. When the IBUF drives a flip-flop within the IOB, the delay element by default activates to ensure a zero hold-time requirement. The NODELAY=TRUE property overrides this default. When the IBUF does not drive a flip-flop within the IOB, the delay element de-activates by default to provide higher performance. To delay the input signal, activate the delay element with the DELAY=TRUE property.
IBUFG I O
x133_03_111699
Figure 39: Virtex-E Global Clock Input Buffer (IBUFG) Symbol The extension to the base name determines which I/O standard is used by the IBUFG. With no extension specified for the generic IBUFG symbol, the assumed standard is LVTTL. The following list details variations of the IBUFG symbol. * * * * * * * * * * * * * * * * * * IBUFG IBUFG_LVCMOS2 IBUFG_PCI33_3 IBUFG_PCI66_3 IBUFG_GTL IBUFG_GTLP IBUFG_HSTL_I IBUFG_HSTL_III IBUFG_HSTL_IV IBUFG_SSTL3_I IBUFG_SSTL3_II IBUFG_SSTL2_I IBUFG_SSTL2_II IBUFG_CTT IBUFG_AGP IBUFG_LVCMOS18 IBUFG_LVDS IBUFG_LVPECL
Bank 0 Bank 7 GCLK3
Bank 1 GCLK2 Bank 2 Bank 3
Virtex-E Device
Bank 6
GCLK1 Bank 5
GCLK0 Bank 4
ds022_42_012100
Figure 38: Virtex-E I/O Banks
Table 19: Rule 1
Xilinx Input Standards Compatibility Requirements Standards with the same input VCCO, output VCCO, and VREF can be placed within the same bank.
When the IBUFG symbol supports an I/O standard that requires a differential amplifier input, the IBUFG automatically configures as a differential amplifier input buffer. The low-voltage I/O standards with a differential amplifier input require an external reference voltage input VREF. The voltage reference signal is "banked" within the Virtex-E device on a half-edge basis such that for all packages there are eight independent VREF banks internally. See Figure 38 for a representation of the Virtex-E I/O banks. Within each bank approximately one of every six I/O pins is automatically configured as a VREF input. After placing a differential amplifier input signal within a given VREF bank, the same external source must drive all I/O pins configured as a VREF input. IBUFG placement restrictions require any differential amplifier input signals within a bank be of the same standard. The LOC property can specify a location for the IBUFG.
IBUFG
Signals used as high fanout clock inputs to the Virtex-E device should drive a global clock input buffer (IBUFG) via an external input port in order to take advantage of one of the four dedicated global clock distribution networks. The output of the IBUFG symbol can only drive a CLKDLL,
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VirtexTM-E 1.8 V Extended Memory Field Programmable Gate Arrays As an added convenience, the BUFGP can be used to instantiate a high fanout clock input. The BUFGP symbol represents a combination of the LVTTL IBUFG and BUFG symbols, such that the output of the BUFGP can connect directly to the clock pins throughout the design. Unlike previous architectures, the Virtex-E BUFGP symbol can only be placed in a global clock pad location. The LOC property can specify a location for the BUFGP. * * * * * * * * * * * * * * * * * * OBUF_F_24 OBUF_LVCMOS2 OBUF_PCI33_3 OBUF_PCI66_3 OBUF_GTL OBUF_GTLP OBUF_HSTL_I OBUF_HSTL_III OBUF_HSTL_IV OBUF_SSTL3_I OBUF_SSTL3_II OBUF_SSTL2_I OBUF_SSTL2_II OBUF_CTT OBUF_AGP OBUF_LVCMOS18 OBUF_LVDS OBUF_LVPECL
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OBUF
An OBUF must drive outputs through an external output port. The generic output buffer (OBUF) symbol appears in Figure 40.
OBUF I O
x133_04_111699
Figure 40: Virtex-E Output Buffer (OBUF) Symbol The extension to the base name defines which I/O standard the OBUF uses. With no extension specified for the generic OBUF symbol, the assumed standard is slew rate limited LVTTL with 12 mA drive strength. The LVTTL OBUF additionally can support one of two slew rate modes to minimize bus transients. By default, the slew rate for each output buffer is reduced to minimize power bus transients when switching non-critical signals. LVTTL output buffers have selectable drive strengths. The format for LVTTL OBUF symbol names is as follows. OBUF__ is either F (Fast), or S (Slow) and is specified in milliamps (2, 4, 6, 8, 12, 16, or 24). The following list details variations of the OBUF symbol. * * * * * * * * * * * * * * OBUF OBUF_S_2 OBUF_S_4 OBUF_S_6 OBUF_S_8 OBUF_S_12 OBUF_S_16 OBUF_S_24 OBUF_F_2 OBUF_F_4 OBUF_F_6 OBUF_F_8 OBUF_F_12 OBUF_F_16
The Virtex-E series supports eight banks for the HQ and PQ packages. The CS packages support four VCCO banks. OBUF placement restrictions require that within a given VCCO bank each OBUF share the same output source drive voltage. Input buffers of any type and output buffers that do not require VCCO can be placed within any VCCO bank. Table 20 summarizes the Virtex-E output compatibility requirements. The LOC property can specify a location for the OBUF. Table 20: Rule 1 Rule 2 VCCO 3.3 2.5 1.5 Output Standards Compatibility Requirements Only outputs with standards that share compatible VCCO can be used within the same bank. There are no placement restrictions for outputs with standards that do not require a VCCO. Compatible Standards LVTTL, SSTL3_I, SSTL3_II, CTT, AGP, GTL, GTL+, PCI33_3, PCI66_3 SSTL2_I, SSTL2_II, LVCMOS2, GTL, GTL+ HSTL_I, HSTL_III, HSTL_IV, GTL, GTL+
OBUFT
The generic 3-state output buffer OBUFT, shown in Figure 41, typically implements 3-state outputs or bidirectional I/O. The extension to the base name defines which I/O standard OBUFT uses. With no extension specified for the generic OBUFT symbol, the assumed standard is slew rate limited LVTTL with 12 mA drive strength.
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VirtexTM-E 1.8 V Extended Memory Field Programmable Gate Arrays The Virtex-E series supports eight banks for the HQ and PQ packages. The CS package supports four VCCO banks. The SelectI/O OBUFT placement restrictions require that within a given VCCO bank each OBUFT share the same output source drive voltage. Input buffers of any type and output buffers that do not require VCCO can be placed within the same VCCO bank. The LOC property can specify a location for the OBUFT. 3-state output buffers and bidirectional buffers can have either a weak pull-up resistor, a weak pull-down resistor, or a weak "keeper" circuit. Control this feature by adding the appropriate symbol to the output net of the OBUFT (PULLUP, PULLDOWN, or KEEPER). The weak "keeper" circuit requires the input buffer within the IOB to sample the I/O signal. So, OBUFTs programmed for an I/O standard that requires a VREF have automatic placement of a VREF in the bank with an OBUFT configured with a weak "keeper" circuit. This restriction does not affect most circuit design as applications using an OBUFT configured with a weak "keeper" typically implement a bidirectional I/O. In this case the IBUF (and the corresponding VREF) are explicitly placed. The LOC property can specify a location for the OBUFT.
The LVTTL OBUFT additionally can support one of two slew rate modes to minimize bus transients. By default, the slew rate for each output buffer is reduced to minimize power bus transients when switching non-critical signals. LVTTL 3-state output buffers have selectable drive strengths. The format for LVTTL OBUFT symbol names is as follows. OBUFT__ can be either F (Fast), or S (Slow) and is specified in milliamps (2, 4, 6, 8, 12, 16, or 24).
T I
OBUFT O
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Figure 41: 3-State Output Buffer Symbol (OBUFT) The following list details variations of the OBUFT symbol. * OBUFT * OBUFT_S_2 * OBUFT_S_4 * OBUFT_S_6 * OBUFT_S_8 * OBUFT_S_12 * OBUFT_S_16 * OBUFT_S_24 * OBUFT_F_2 * OBUFT_F_4 * OBUFT_F_6 * OBUFT_F_8 * OBUFT_F_12 * OBUFT_F_16 * OBUFT_F_24 * OBUFT_LVCMOS2 * OBUFT_PCI33_3 * OBUFT_PCI66_3 * OBUFT_GTL * OBUFT_GTLP * OBUFT_HSTL_I * OBUFT_HSTL_III * OBUFT_HSTL_IV * OBUFT_SSTL3_I * OBUFT_SSTL3_II * OBUFT_SSTL2_I * OBUFT_SSTL2_II * OBUFT_CTT * OBUFT_AGP * OBUFT_LVCMOS18 * OBUFT_LVDS * OBUFT_LVPECL
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IOBUF
Use the IOBUF symbol for bidirectional signals that require both an input buffer and a 3-state output buffer with an active high 3-state pin. The generic input/output buffer IOBUF appears in Figure 42. The extension to the base name defines which I/O standard the IOBUF uses. With no extension specified for the generic IOBUF symbol, the assumed standard is LVTTL input buffer and slew rate limited LVTTL with 12 mA drive strength for the output buffer. The LVTTL IOBUF additionally can support one of two slew rate modes to minimize bus transients. By default, the slew rate for each output buffer is reduced to minimize power bus transients when switching non-critical signals. LVTTL bidirectional buffers have selectable output drive strengths. The format for LVTTL IOBUF symbol names is as follows. IOBUF__ can be either F (Fast), or S (Slow) and is specified in milliamps (2, 4, 6, 8, 12, 16, or 24).
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T I
IOBUF IO
O
The voltage reference signal is "banked" within the Virtex-E device on a half-edge basis such that for all packages there are eight independent VREF banks internally. See Figure 38 on page 33 for a representation of the Virtex-E I/O banks. Within each bank approximately one of every six I/O pins is automatically configured as a VREF input. After placing a differential amplifier input signal within a given VREF bank, the same external source must drive all I/O pins configured as a VREF input. IOBUF placement restrictions require any differential amplifier input signals within a bank be of the same standard. The Virtex-E series supports eight banks for the HQ and PQ packages. The CS package supports four VCCO banks. Additional restrictions on the Virtex-E SelectI/O IOBUF placement require that within a given VCCO bank each IOBUF must share the same output source drive voltage. Input buffers of any type and output buffers that do not require VCCO can be placed within the same VCCO bank. The LOC property can specify a location for the IOBUF. An optional delay element is associated with the input path in each IOBUF. When the IOBUF drives an input flip-flop within the IOB, the delay element activates by default to ensure a zero hold-time requirement. Override this default with the NODELAY=TRUE property. In the case when the IOBUF does not drive an input flip-flop within the IOB, the delay element de-activates by default to provide higher performance. To delay the input signal, activate the delay element with the DELAY=TRUE property. 3-state output buffers and bidirectional buffers can have either a weak pull-up resistor, a weak pull-down resistor, or a weak "keeper" circuit. Control this feature by adding the appropriate symbol to the output net of the IOBUF (PULLUP, PULLDOWN, or KEEPER).
x133_06_111699
Figure 42: Input/Output Buffer Symbol (IOBUF) The following list details variations of the IOBUF symbol. * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * IOBUF IOBUF_S_2 IOBUF_S_4 IOBUF_S_6 IOBUF_S_8 IOBUF_S_12 IOBUF_S_16 IOBUF_S_24 IOBUF_F_2 IOBUF_F_4 IOBUF_F_6 IOBUF_F_8 IOBUF_F_12 IOBUF_F_16 IOBUF_F_24 IOBUF_LVCMOS2 IOBUF_PCI33_3 IOBUF_PCI66_3 IOBUF_GTL IOBUF_GTLP IOBUF_HSTL_I IOBUF_HSTL_III IOBUF_HSTL_IV IOBUF_SSTL3_I IOBUF_SSTL3_II IOBUF_SSTL2_I IOBUF_SSTL2_II IOBUF_CTT IOBUF_AGP IOBUF_LVCMOS18 IOBUF_LVDS IOBUF_LVPECL
SelectI/O Properties
Access to some of the SelectI/O features (for example, location constraints, input delay, output drive strength, and slew rate) is available through properties associated with these features.
Input Delay Properties
An optional delay element is associated with each IBUF. When the IBUF drives a flip-flop within the IOB, the delay element activates by default to ensure a zero hold-time requirement. Use the NODELAY=TRUE property to override this default. In the case when the IBUF does not drive a flip-flop within the IOB, the delay element by default de-activates to provide higher performance. To delay the input signal, activate the delay element with the DELAY=TRUE property.
When the IOBUF symbol used supports an I/O standard that requires a differential amplifier input, the IOBUF automatically configures with a differential amplifier input buffer. The low-voltage I/O standards with a differential amplifier input require an external reference voltage input VREF.
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VirtexTM-E 1.8 V Extended Memory Field Programmable Gate Arrays
IOB Flip-Flop/Latch Property
The Virtex-E series I/O block (IOB) includes an optional register on the input path, an optional register on the output path, and an optional register on the 3-state control pin. The design implementation software automatically takes advantage of these registers when the following option for the Map program is specified. map -pr b Alternatively, the IOB = TRUE property can be placed on a register to force the mapper to place the register in an IOB.
Design Considerations
Reference Voltage (VREF) Pins
Low-voltage I/O standards with a differential amplifier input buffer require an input reference voltage (VREF). Provide the VREF as an external signal to the device. The voltage reference signal is "banked" within the device on a half-edge basis such that for all packages there are eight independent VREF banks internally. See Figure 38 for a representation of the Virtex-E I/O banks. Within each bank approximately one of every six I/O pins is automatically configured as a VREF input. After placing a differential amplifier input signal within a given VREF bank, the same external source must drive all I/O pins configured as a VREF input. Within each VREF bank, any input buffers that require a VREF signal must be of the same type. Output buffers of any type and input buffers can be placed without requiring a reference voltage within the same VREF bank.
Location Constraints
Specify the location of each SelectI/O symbol with the location constraint LOC attached to the SelectI/O symbol. The external port identifier indicates the value of the location constrain. The format of the port identifier depends on the package chosen for the specific design. The LOC properties use the following form. LOC=A42 LOC=P37
Output Drive Source Voltage (VCCO) Pins
Many of the low voltage I/O standards supported by SelectI/O devices require a different output drive source voltage (VCCO). As a result each device can often have to support multiple output drive source voltages. The Virtex-E series supports eight banks for the HQ and PQ packages. The CS package supports four VCCO banks. Output buffers within a given VCCO bank must share the same output drive source voltage. Input buffers for LVTTL, LVCMOS2, LVCMOS18, PCI33_3, and PCI 66_3 use the VCCO voltage for Input VCCO voltage.
Output Slew Rate Property
As mentioned above, a variety of symbol names provide the option of choosing the desired slew rate for the output buffers. In the case of the LVTTL output buffers (OBUF, OBUFT, and IOBUF), slew rate control can be alternatively programed with the SLEW= property. By default, the slew rate for each output buffer is reduced to minimize power bus transients when switching non-critical signals. The SLEW= property has one of the two following values. SLEW=SLOW SLEW=FAST
Transmission Line Effects
The delay of an electrical signal along a wire is dominated by the rise and fall times when the signal travels a short distance. Transmission line delays vary with inductance and capacitance, but a well-designed board can experience delays of approximately 180 ps per inch. Transmission line effects, or reflections, typically start at 1.5" for fast (1.5 ns) rise and fall times. Poor (or non-existent) termination or changes in the transmission line impedance cause these reflections and can cause additional delay in longer traces. As system speeds continue to increase, the effect of I/O delays can become a limiting factor and therefore transmission line termination becomes increasingly more important.
Output Drive Strength Property
The desired output drive strength can be additionally specified by choosing the appropriate library symbol. The Xilinx library also provides an alternative method for specifying this feature. For the LVTTL output buffers (OBUF, OBUFT, and IOBUF, the desired drive strength can be specified with the DRIVE= property. This property could have one of the following seven values. DRIVE=2 DRIVE=4 DRIVE=6 DRIVE=8 DRIVE=12 (Default) DRIVE=16 DRIVE=24
Termination Techniques
A variety of termination techniques reduce the impact of transmission line effects. The following are output termination techniques: * * * * None Series Parallel (Shunt) Series and Parallel (Series-Shunt)
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VirtexTM-E 1.8 V Extended Memory Field Programmable Gate Arrays Input termination techniques include the following: * * None Parallel (Shunt) Table 21: Guidelines for Maximum Number of Simultaneously Switching Outputs per Power/Ground Pair Package Standard LVTTL Slow Slew Rate, 2 mA drive LVTTL Slow Slew Rate, 4 mA drive
Z=50 VREF
R
These termination techniques can be applied in any combination. A generic example of each combination of termination methods appears in Figure 43.
Unterminated
Z=50
BGA, FGA 68 41 29 22 17 14 9 40 24 17 13 10 8 5 10 8 4 4 18 9 5 15 10 11 7 14 9
Double Parallel Terminated
VTT VTT
LVTTL Slow Slew Rate, 6 mA drive
VTT
Unterminated Output Driving a Parallel Terminated Input
VTT
Series Terminated Output Driving a Parallel Terminated Input
LVTTL Slow Slew Rate, 8 mA drive LVTTL Slow Slew Rate, 12 mA drive LVTTL Slow Slew Rate, 16 mA drive
Z=50 VREF
Z=50 VREF
Series-Parallel Terminated Output Driving a Parallel Terminated Input Series Terminated Output
Z=50 Z=50 VREF VREF
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VTT
VTT
LVTTL Slow Slew Rate, 24 mA drive LVTTL Fast Slew Rate, 2 mA drive LVTTL Fast Slew Rate, 4 mA drive LVTTL Fast Slew Rate, 6 mA drive LVTTL Fast Slew Rate, 8 mA drive LVTTL Fast Slew Rate, 12 mA drive LVTTL Fast Slew Rate, 16 mA drive LVTTL Fast Slew Rate, 24 mA drive LVCMOS2 PCI GTL GTL+ HSTL Class I HSTL Class III HSTL Class IV SSTL2 Class I SSTL2 Class II SSTL3 Class I SSTL3 Class II CTT AGP
Figure 43: Overview of Standard Input and Output Termination Methods
Simultaneous Switching Guidelines
Ground bounce can occur with high-speed digital ICs when multiple outputs change states simultaneously, causing undesired transient behavior on an output, or in the internal logic. This problem is also referred to as the Simultaneous Switching Output (SSO) problem. Ground bounce is primarily due to current changes in the combined inductance of ground pins, bond wires, and ground metallization. The IC internal ground level deviates from the external system ground level for a short duration (a few nanoseconds) after multiple outputs change state simultaneously. Ground bounce affects stable Low outputs and all inputs because they interpret the incoming signal by comparing it to the internal ground. If the ground bounce amplitude exceeds the actual instantaneous noise margin, then a non-changing input can be interpreted as a short pulse with a polarity opposite to the ground bounce. Table 21 provides the guidelines for the maximum number of simultaneously switching outputs allowed per output power/ground pair to avoid the effects of ground bounce. Refer to Table 22 for the number of effective output power/ground pairs for each Virtex-E device and package combination.
Note: This analysis assumes a 35 pF load for each output.
Table 22:
Virtex-E Extended Memory Family Equivalent Power/Ground Pairs Pkg/Part BG560 FG676 FG900 56 XCV405E XCV812E 56
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VirtexTM-E 1.8 V Extended Memory Field Programmable Gate Arrays Table 23: GTL Voltage Specifications Min 0.74 1.14 0.79 32 Typ N/A 0.8 1.2 0.85 0.75 0.2 Max 0.86 1.26 0.81 0.4 40
Application Examples
Creating a design with the SelectI/O features requires the instantiation of the desired library symbol within the design code. At the board level, designers need to know the termination techniques required for each I/O standard. This section describes some common application examples illustrating the termination techniques recommended by each of the standards supported by the SelectI/O features.
Parameter VCCO VREF = N x VTT1 VTT VIH = VREF + 0.05 VIL = VREF - 0.05 VOH VOL IOH at VOH(mA) IOLat VOL(mA) at 0.4V IOLat VOL(mA) at 0.2V
Termination Examples
Circuit examples involving typical termination techniques for each of the SelectI/O standards follow. For a full range of accepted values for the DC voltage specifications for each standard, refer to the table associated with each figure. The resistors used in each termination technique example and the transmission lines depicted represent board level components and are not meant to represent components on the device. GTL A sample circuit illustrating a valid termination technique for GTL is shown in Figure 44. Table 23 lists DC voltage specifications.
Note: N must be greater than or equal to 0.653 and less than or equal to 0.68.
GTL+ A sample circuit illustrating a valid termination technique for GTL+ appears in Figure 45. DC voltage specifications appear in Table 24.
GTL VTT = 1.2V 50 VCCO = N/A VTT = 1.2V 50
Z = 50
GTL+ VTT = 1.5V VTT = 1.5V 50
VCCO = N/A
Z = 50
50
VREF = 0.8V
x133_08_111699
VREF = 1.0V
x133_09_012400
Figure 44: Terminated GTL Table 24:
Figure 45: Terminated GTL+
GTL+ Voltage Specifications Min 0.88 1.35 0.98 0.3 36 Typ 1.0 1.5 1.1 0.9 0.45 Max 1.12 1.65 1.02 0.6 48
Parameter VCCO VREF = N x VTT1 VTT VIH = VREF + 0.1 VIL = VREF - 0.1 VOH VOL IOH at VOH (mA) IOLat VOL (mA) at 0.6V IOLat VOL (mA) at 0.3V
Note: N must be greater than or equal to 0.653 and less than or equal to 0.68.
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HSTL
A sample circuit illustrating a valid termination technique for HSTL_I appears in Figure 46. A sample circuit illustrating a valid termination technique for HSTL_III appears in Figure 47.
HSTL Class I VCCO = 1.5V VTT= 0.75V 50
Z = 50
Table 26:
HSTL Class III Voltage Specification Min 1.40 VREF + 0.1 VCCO - 0.4 -8 24 Typ 1.50 0.90 VCCO Max 1.60 VREF - 0.1 0.4 -
Parameter VCCO VREF (1) VTT VIH VIL VOH
VREF = 0.75V
x133_10_111699
VOL IOH at VOH (mA) IOLat VOL (mA)
Figure 46: Terminated HSTL Class I
Table 25:
HSTL Class I Voltage Specification Min 1.40 0.68 VREF + 0.1 VCCO - 0.4 -8 8 Typ 1.50 0.75 VCCO x 0.5 Max 1.60 0.90 VREF - 0.1 0.4 -
Parameter VCCO VREF VTT VIH VIL VOH VOL IOH at VOH (mA) IOLat VOL (mA)
Note: Per EIA/JESD8-6, "The value of VREF is to be selected by the user to provide optimum noise margin in the use conditions specified by the user."
A sample circuit illustrating a valid termination technique for HSTL_IV appears in Figure 48.
HSTL Class IV VCCO = 1.5V VTT= 1.5V VTT= 1.5V 50 50
Z = 50
VREF = 0.9V
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Figure 48: Terminated HSTL Class IV
Table 27:
HSTL Class III VCCO = 1.5V VTT= 1.5V 50
Z = 50
HSTL Class IV Voltage Specification Min 1.40 VREF + 0.1 VCCO - 0.4 -8 48 Typ 1.50 0.90 VCCO Max 1.60 VREF - 0.1 0.4 -
Parameter VCCO VREF VTT VIH
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VREF = 0.9V
Figure 47: Terminated HSTL Class III
VIL VOH VOL IOH at VOH (mA) IOLat VOL (mA)
Note: Per EIA/JESD8-6, "The value of VREF is to be selected by the user to provide optimum noise margin in the use conditions specified by the user.
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VirtexTM-E 1.8 V Extended Memory Field Programmable Gate Arrays Table 29: SSTL3_II Voltage Specifications Parameter VCCO VREF = 0.45 x VCCO
VTT= 1.5V 50
Z = 50
SSTL3_I
A sample circuit illustrating a valid termination technique for SSTL3_I appears in Figure 49. DC voltage specifications appear in Table 28.
SSTL3 Class I VCCO = 3.3V 25
Min 3.0 1.3 1.3 1.5 -0.3(2) 2.1 -16 16
Typ 3.3 1.5 1.5 1.7 1.3 -
Max 3.6 1.7 1.7 3.9(1) 1.5 0.9 -
VTT = VREF VIH = VREF + 0.2 VIL= VREF - 0.2 VOH = VREF + 0.8
VREF = 1.5V
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VOL= VREF - 0.8 IOH at VOH (mA) IOLat VOL (mA)
Figure 49: Terminated SSTL3 Class I
Table 28:
SSTL3_I Voltage Specifications Parameter Min 3.0 1.3 1.3 1.5 -0.3(2) 1.9 -8 8 Typ 3.3 1.5 1.5 1.7 1.3 Max 3.6 1.7 1.7 3.9(1) 1.5 1.1 -
Notes: 1. VIH maximum is VCCO + 0.3 2. VIL minimum does not conform to the formula
VCCO VREF = 0.45 x VCCO VTT = VREF VIH = VREF + 0.2 VIL = VREF - 0.2 VOH = VREF + 0.6 VOL = VREF - 0.6 IOH at VOH (mA) IOLat VOL (mA)
SSTL2_I
A sample circuit illustrating a valid termination technique for SSTL2_I appears in Figure 51. DC voltage specifications appear in Table 30.
SSTL2 Class I
VCCO = 2.5V 25
Z = 50
VTT= 1.25V 50
V
REF
= 1.25V
xap133_15_011000
Figure 51: Terminated SSTL2 Class I Table 30: SSTL2_I Voltage Specifications Parameter VCCO VREF = 0.5 x VCCO VTT = VREF + N(1) VIH = VREF + 0.18 VIL = VREF - 0.18 VOH = VREF + 0.61 VOL= VREF - 0.61
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Notes: 1. VIH maximum is VCCO + 0.3 2. VIL minimum does not conform to the formula
SSTL3_II
A sample circuit illustrating a valid termination technique for SSTL3_II appears in Figure 50. DC voltage specifications appear in Table 29.
SSTL3 Class II VCCO = 3.3V 25 VTT= 1.5V VTT= 1.5V 50 50
Z = 50
Min 2.3 1.15 1.11 1.33 -0.3(3) 1.76 -7.6 7.6
Typ 2.5 1.25 1.25 1.43 1.07 -
Max 2.7 1.35 1.39 3.0(2) 1.17 0.74 -
VREF = 1.5V
IOH at VOH (mA) IOLat VOL (mA)
Figure 50: Terminated SSTL3 Class II
Notes: 1. N must be greater than or equal to -0.04 and less than or equal to 0.04. 2. VIH maximum is VCCO + 0.3. 3. VIL minimum does not conform to the formula.
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SSTL2_II
A sample circuit illustrating a valid termination technique for SSTL2_II appears in Figure 52. DC voltage specifications appear in Table 31. Table 32: CTT Voltage Specifications Min 2.05(1) 1.35 1.35 1.55 1.75 -8 8 Typ 3.3 1.5 1.5 1.7 1.3 1.9 1.1 Max 3.6 1.65 1.65 1.45 1.25 Parameter VCCO VREF VTT VIH = VREF + 0.2 VIL = VREF - 0.2
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SSTL2 Class II VCCO = 2.5V 25 VTT= 1.25V VTT= 1.25V 50 50
Z = 50
VREF = 1.25V
Figure 52: Terminated SSTL2 Class II
VOH = VREF + 0.4 VOL= VREF - 0.4 IOH at VOH (mA)
Table 31:
SSTL2_II Voltage Specifications Min 2.3 1.15 1.11 1.33 -0.3(3) 1.95 -15.2 15.2 Typ 2.5 1.25 1.25 1.43 1.07 Max 2.7 1.35 1.39 3.0(2)
IOLat VOL (mA)
Parameter VCCO VREF = 0.5 x VCCO VTT = VREF + N (1) VIH = VREF + 0.18 VIL = VREF - 0.18 VOH = VREF + 0.8 VOL = VREF - 0.8 IOH at VOH (mA) IOLat VOL (mA)
Notes: 1. Timing delays are calculated based on VCCO min of 3.0V.
PCI33_3 & PCI66_3
PCI33_3 or PCI66_3 require no termination. DC voltage specifications appear in Table 33. Table 33: PCI33_3 and PCI66_3 Voltage Specifications Min 3.0 1.5 -0.5 2.7 Note 1 Note 1 Typ 3.3 1.65 0.99 Max 3.6 VCCO+ 0.5 1.08 0.36 -
1.17 0.55 VCCO VREF VTT
Parameter
Notes: 1. N must be greater than or equal to -0.04 and less than or equal to 0.04. 2. VIH maximum is VCCO + 0.3. 3. VIL minimum does not conform to the formula.
VIH = 0.5 x VCCO VIL = 0.3 x VCCO VOH = 0.9 x VCCO VOL= 0.1 x VCCO IOH at VOH (mA) IOLat VOL (mA)
CTT
A sample circuit illustrating a valid termination technique for CTT appear in Figure 53. DC voltage specifications appear in Table 32.
Note 1: Tested according to the relevant specification.
CTT VCCO = 3.3V VTT = 1.5V 50
Z = 50
VREF= 1.5V
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Figure 53: Terminated CTT
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LVTTL
LVTTL requires no termination. DC voltage specifications appears in Table 34. Table 34: LVTTL Voltage Specifications Min 3.0 2.0 -0.5 2.4 -24 24 Typ 3.3 Max 3.6 3.6 0.8 0.4 -
LVCMOS18
LVCMOS18 does not require termination. Table 36 lists DC voltage specifications. Table 36: LVCMOS18 Voltage Specifications Min 1.70 0.7 x VCCO - 0.5 VCCO - 0.4 -8 8 Typ 1.80 Max 1.90 1.95 0.2 x VCCO 0.4 -
Parameter VCCO VREF VTT VIH VIL VOH VOL IOH at VOH (mA) IOLat VOL (mA)
Parameter VCCO VREF VTT VIH VIL VOH VOL IOH at VOH (mA) IOLat VOL (mA)
Note: VOLand VOH for lower drive currents sample tested.
AGP-2X LVCMOS2
LVCMOS2 requires no termination. DC voltage specifications appear in Table 35. Table 35: LVCMOS2 Voltage Specifications Min 2.3 1.7 -0.5 1.9 -12 12 Typ 2.5 Max 2.7 3.6 0.7 0.4 VCCO VREF = N x VCCO(1) VTT VIH = VREF + 0.2 VIL = VREF - 0.2 VOH = 0.9 x VCCO VOL = 0.1 x VCCO IOH at VOH (mA) IOLat VOL (mA) The specification for the AGP-2X standard does not document a recommended termination technique. DC voltage specifications appear in Table 37. Table 37: AGP-2X Voltage Specifications Parameter Min 3.0 1.17 1.37 2.7 Note 2 Note 2 Typ 3.3 1.32 1.52 1.12 3.0 0.33 Max 3.6 1.48 1.28 0.36 -
Parameter VCCO VREF VTT VIH VIL VOH VOL IOH at VOH (mA) IOLat VOL (mA)
Notes: 1. N must be greater than or equal to 0.39 and less than or equal to 0.41. 2. Tested according to the relevant specification.
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LVDS
Depending on whether the device is transmitting an LVDS signal or receiving an LVDS signal, there are two different circuits used for LVDS termination. A sample circuit illustrating a valid termination technique for transmitting LVDS signals appears in Figure 54. A sample circuit illustrating a valid termination for receiving LVDS signals appears in Figure 55. Table 38 lists DC voltage specifications. Further information on the specific termination resistor packs shown can be found on Table 40.
LVPECL
Depending on whether the device is transmitting or receiving an LVPECL signal, two different circuits are used for LVPECL termination. A sample circuit illustrating a valid termination technique for transmitting LVPECL signals appears in Figure 56. A sample circuit illustrating a valid termination for receiving LVPECL signals appears in Figure 57. Table 39 lists DC voltage specifications. Further information on the specific termination resistor packs shown can be found on Table 40.
1/4 of Bourns Part Number CAT16-PC4F12 Q 3.3V RS 100 RDIV 187 Z0 = 50 LVPECL_OUT to LVPECL Receiver Z0 = 50 LVPECL_OUT to LVPECL Receiver
Virtex-E FPGA Q 2.5V DATA Transmit Q VCCO = 2.5V LVDS Output
1/4 of Bourns Part Number CAT16-LV4F12 RS 165 RDIV 140 Z0 = 50 to LVDS Receiver Z0 = 50 to LVDS Receiver
Virtex-E FPGA
DATA Transmit Q
RS 100
RS 165
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Figure 56: Transmitting LVPECL Signal Circuit
x133_19_122799
Figure 54: Transmitting LVDS Signal Circuit
Q Z0 = 50 LVPECL_IN + RT 100 Z0 = 50 Q LVPECL_IN DATA Receive
VIRTEX-E FPGA
Q
Z0 = 50
LVDS_IN + RT 100
VIRTEX-E FPGA
from LVPECL Driver
-
from LVDS Driver
Z0 = 50 Q
-
DATA Receive
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LVDS_IN
Figure 57: Receiving LVPECL Signal Circuit
x133_29_122799
Figure 55: Receiving LVDS Signal Circuit
Table 39:
LVPECL Voltage Specifications Min 3.0 1.49 0.86 1.8 Typ 3.3 Max 3.6 2.72 2.125 1.57
Parameter Table 38: LVDS Voltage Specifications Min 2.375 0.2 1.125 0.1 0.25 1.25 Typ 2.5 1.25 1.25 0.35 0.35 Max 2.625 2.2 1.375 0.45 1.25 VCCO VREF VTT VIH VIL VOH VOL Parameter VCCO VICM(2) VOCM(1) VIDIFF (1) VODIFF (1) VOH(1) VOL(1)
Note: For more detailed information, see LVPECL DC Specifications
Notes: 1. Measured with a 100 resistor across Q and Q. 2. Measured with a differential input voltage = +/- 350 mV.
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Termination Resistor Packs
Resistor packs are available with the values and the configuration required for LVDS and LVPECL termination from Bourns, Inc., as listed in Table. For pricing and availability, please contact Bourns directly at www.bourns.com. Table 40: Bourns LVDS/LVPECL Resistor Packs
I/O Standard LVDS LVDS LVPECL LVPECL LVDS/LVPECL LVDS/LVPECL Term. for: Driver Driver Driver Driver Receiver Receiver Pairs/ Pack 2 4 2 4 2 4 Pins 8 16 8 16 8 16
HDL Instantiation
Only one global clock input buffer is required to be instantiated in the design and placed on the correct GCLKPAD location. The N-side of the buffer is reserved and no other IOB is allowed to be placed on this location. In the physical device, a configuration option is enabled that routes the pad wire to the differential input buffer located in the GCLKIOB. The output of this buffer then drives the output of the GCLKIOB cell. In EPIC it appears that the second buffer is unused. Any attempt to use this location for another purpose leads to a DRC error in the software. VHDL Instantiation gclk0_p : IBUFG_LVDS port map (I=>clk_external, O=>clk_internal); Verilog Instantiation IBUFG_LVDS gclk0_p (.I(clk_external), .O(clk_internal));
Part Number CAT16-LV2F6 CAT16-LV4F12 CAT16-PC2F6 CAT16-PC4F12 CAT16-PT2F2 CAT16-PT4F4
Location Constraints
LVDS Design Guide
The SelectI/O library elements have been expanded for Virtex-E devices to include new LVDS variants. At this time all of the cells might not be included in the Synthesis libraries. The 2.1i-Service Pack 2 update for Alliance and Foundation software includes these cells in the VHDL and Verilog libraries. It is necessary to combine these cells to create the P-side (positive) and N-side (negative) as described in the input, output, 3-state and bidirectional sections.
IBUF_LVDS I O OBUF_LVDS I O IOBUF_LVDS T I IBUFG_LVDS I O OBUFT_LVDS T I O IO
All LVDS buffers must be explicitly placed on a device. For the global clock input buffers this can be done with the following constraint in the UCF or NCF file. NET clk_external LOC = GCLKPAD3; GCLKPAD3 can also be replaced with the package pin name, such as D17 for the BG432 package.
Optional N-Side
Some designers might prefer to also instantiate the N-side buffer for the global clock buffer. This allows the top-level net list to include net connections for both PCB layout and system-level integration. In this case, only the output P-side IBUFG connection has a net connected to it. Since the N-side IBUFG does not have a connection in the EDIF net list, it is trimmed from the design in MAP. VHDL Instantiation
O
x133_22_122299
Figure 58: LVDS Elements
gclk0_p : IBUFG_LVDS port map (I=>clk_p_external, O=>clk_internal); gclk0_n : IBUFG_LVDS port map (I=>clk_n_external, O=>clk_internal); Verilog Instantiation IBUFG_LVDS gclk0_p (.I(clk_p_external), .O(clk_internal)); IBUFG_LVDS gclk0_n (.I(clk_n_external), .O(clk_internal));
Creating LVDS Global Clock Input Buffers
The global clock input buffer can be combined with the adjacent IOB to form an LVDS clock input buffer. The P-side resides in the GCLKPAD location and the N-side resides in the adjacent IO_LVDS_DLL site. Table 41: Global Clock Input Buffer Pair Locations
Pair 3 Pkg
BG560 FG676 FG900
Pair 2 P
D17 C13 E15
Pair 2 P
AJ17 AB13 AK16
Pair 0 P
AL17 AA14 AJ16
Location Constraints
All LVDS buffers must be explicitly placed on a device. For the global clock input buffers this can be done with the following constraint in the UCF or NCF file. NET clk_p_external LOC = GCLKPAD3; NET clk_n_external LOC = C17;
P
A17 E13 C15
N
C18 B13 A15
N
E17 F14 E16
N
AM18 AF13 AH16
N
AM17 AC14 AF16
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Location Constraints
All LVDS buffers must be explicitly placed on a device. For the global clock input buffers this can be done with the following constraint in the UCF or NCF file. NET data_p<0> LOC = D28; # IO_L0P NET data_n<0> LOC = B29; # IO_L0N
Creating LVDS Input Buffers
An LVDS input buffer can be placed in a wide number of IOB locations. The exact location is dependent on the package that is used. The Virtex-E package information lists the possible locations as IO_L#P for the P-side and IO_L#N for the N-side where # is the pair number.
Adding an Input Register
All LVDS buffers can have an input register in the IOB. The input register is in the P-side IOB only. All the normal IOB register options are available (FD, FDE, FDC, FDCE, FDP, FDPE, FDR, FDRE, FDS, FDSE, LD, LDE, LDC, LDCE, LDP, LDPE). The register elements can be inferred or explicitly instantiated in the HDL code. The register elements can be packed in the IOB using the IOB property to TRUE on the register or by using "map -pr [i|o|b]", where "i" is inputs only, "o" is outputs only, and "b" is both inputs and outputs. To improve design coding times VHDL and Verilog synthesis macro libraries available to explicitly create these structures. The input library macros are listed in Table 42. The I and IB inputs to the macros are the external net connections. Table 42: Input Library Macros Name IBUFDS_FD_LVDS IBUFDS_FDE_LVDS IBUFDS_FDC_LVDS IBUFDS_FDCE_LVDS IBUFDS_FDP_LVDS IBUFDS_FDPE_LVDS IBUFDS_FDR_LVDS IBUFDS_FDRE_LVDS IBUFDS_FDS_LVDS IBUFDS_FDSE_LVDS IBUFDS_LD_LVDS IBUFDS_LDE_LVDS IBUFDS_LDC_LVDS IBUFDS_LDCE_LVDS IBUFDS_LDP_LVDS IBUFDS_LDPE_LVDS Inputs I, IB, C I, IB, CE, C I, IB, C, CLR I, IB, CE, C, CLR I, IB, C, PRE I, IB, CE, C, PRE I, IB, C, R I, IB, CE, C, R I, IB, C, S I, IB, CE, C, S I, IB, G I, IB, GE, G I, IB, G, CLR I, IB, GE, G, CLR I, IB, G, PRE I, IB, GE, G, PRE Outputs Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q
HDL Instantiation
Only one input buffer is required to be instantiated in the design and placed on the correct IO_L#P location. The N-side of the buffer is reserved and no other IOB is allowed to be placed on this location. In the physical device, a configuration option is enabled that routes the pad wire from the IO_L#N IOB to the differential input buffer located in the IO_L#P IOB. The output of this buffer then drives the output of the IO_L#P cell or the input register in the IO_L#P IOB. In EPIC it appears that the second buffer is unused. Any attempt to use this location for another purpose leads to a DRC error in the software. VHDL Instantiation data0_p : IBUF_LVDS port map (I=>data(0), O=>data_int(0)); Verilog Instantiation IBUF_LVDS data0_p (.I(data[0]), .O(data_int[0]));
Location Constraints
All LVDS buffers must be explicitly placed on a device. For the input buffers this can be done with the following constraint in the UCF or NCF file. NET data<0> LOC = D28; # IO_L0P
Optional N-side
Some designers might prefer to also instantiate the N-side buffer for the input buffer. This allows the top-level net list to include net connections for both PCB layout and system-level integration. In this case, only the output P-side IBUF connection has a net connected to it. Since the N-side IBUF does not have a connection in the EDIF net list, it is trimmed from the design in MAP. VHDL Instantiation data0_p : IBUF_LVDS port map (I=>data_p(0), O=>data_int(0)); data0_n : IBUF_LVDS port map (I=>data_n(0), O=>open); Verilog Instantiation IBUF_LVDS data0_p (.I(data_p[0]), .O(data_int[0])); IBUF_LVDS data0_n (.I(data_n[0]), .O());
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VirtexTM-E 1.8 V Extended Memory Field Programmable Gate Arrays some point in the product lifetime, then only the common pairs for all packages should be used.
Creating LVDS Output Buffers
LVDS output buffer can be placed in wide number of IOB locations. The exact location are dependent on the package that is used. The Virtex-E package information lists the possible locations as IO_L#P for the P-side and IO_L#N for the N-side where # is the pair number.
Adding an Output Register
All LVDS buffers can have an output register in the IOB. The output registers must be in both the P-side and N-side IOBs. All the normal IOB register options are available (FD, FDE, FDC, FDCE, FDP, FDPE, FDR, FDRE, FDS, FDSE, LD, LDE, LDC, LDCE, LDP, LDPE). The register elements can be inferred or explicitly instantiated in the HDL code. Special care must be taken to insure that the D pins of the registers are inverted and that the INIT states of the registers are opposite. The clock pin (C), clock enable (CE) and set/reset (CLR/PRE or S/R) pins must connect to the same source. Failure to do this leads to a DRC error in the software. The register elements can be packed in the IOB using the IOB property to TRUE on the register or by using the "map -pr [i|o|b]" where "i" is inputs only, "o" is outputs only and "b" is both inputs and outputs. To improve design coding times VHDL and Verilog synthesis macro libraries have been developed to explicitly create these structures. The output library macros are listed in Table 43. The O and OB inputs to the macros are the external net connections. Table 43: Output Library Macros Name OBUFDS_FD_LVDS OBUFDS_FDE_LVDS OBUFDS_FDC_LVDS OBUFDS_FDCE_LVDS OBUFDS_FDP_LVDS OBUFDS_FDPE_LVDS OBUFDS_FDR_LVDS OBUFDS_FDRE_LVDS OBUFDS_FDS_LVDS OBUFDS_FDSE_LVDS OBUFDS_LD_LVDS OBUFDS_LDE_LVDS OBUFDS_LDC_LVDS OBUFDS_LDCE_LVDS OBUFDS_LDP_LVDS OBUFDS_LDPE_LVDS Inputs D, C DD, CE, C D, C, CLR D, CE, C, CLR D, C, PRE D, CE, C, PRE D, C, R D, CE, C, R D, C, S D, CE, C, S D, G D, GE, G D, G, CLR D, GE, G, CLR D, G, PRE D, GE, G, PRE Outputs O, OB O, OB O, OB O, OB O, OB O, OB O, OB O, OB O, OB O, OB O, OB O, OB O, OB O, OB O, OB O, OB
HDL Instantiation
Both output buffers are required to be instantiated in the design and placed on the correct IO_L#P and IO_L#N locations. The IOB must have the same net source the following pins, clock (C), set/reset (SR), output (O), output clock enable (OCE). In addition, the output (O) pins must be inverted with respect to each other, and if output registers are used, the INIT states must be opposite values (one HIGH and one LOW). Failure to follow these rules leads to DRC errors in software. VHDL Instantiation data0_p : OBUF_LVDS port map (I=>data_int(0), O=>data_p(0)); data0_inv: INV (I=>data_int(0), port map O=>data_n_int(0));
data0_n : OBUF_LVDS port map (I=>data_n_int(0), O=>data_n(0)); Verilog Instantiation OBUF_LVDS data0_p .O(data_p[0])); (.I(data_int[0]),
INV data0_inv (.I(data_int[0], .O(data_n_int[0]); OBUF_LVDS data0_n .O(data_n[0])); (.I(data_n_int[0]),
Location Constraints
All LVDS buffers must be explicitly placed on a device. For the output buffers this can be done with the following constraint in the UCF or NCF file. NET data_p<0> LOC = D28; # IO_L0P NET data_n<0> LOC = B29; # IO_L0N
Synchronous vs. Asynchronous Outputs
If the outputs are synchronous (registered in the IOB), then any IO_L#P|N pair can be used. If the outputs are asynchronous (no output register), then they must use one of the pairs that are part of the same IOB group at the end of a ROW or at the top/bottom of a COLUMN in the device. The LVDS pairs that can be used as asynchronous outputs are listed in the Virtex-E pinout tables. Some pairs are marked as asynchronous-capable for all devices in that package, and others are marked as available only for that device in the package. If the device size might change at
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Creating LVDS Output 3-State Buffers
LVDS output 3-state buffers can be placed in a wide number of IOB locations. The exact locations are dependent on the package used. The Virtex-E package information lists the possible locations as IO_L#P for the P-side and IO_L#N for the N-side, where # is the pair number.
LVDS pairs that can be used as asynchronous outputs are listed in the Virtex-E pinout tables. Some pairs are marked as "asynchronous capable" for all devices in that package, and others are marked as available only for that device in the package. If the device size might be changed at some point in the product lifetime, then only the common pairs for all packages should be used.
HDL Instantiation
Both output 3-state buffers are required to be instantiated in the design and placed on the correct IO_L#P and IO_L#N locations. The IOB must have the same net source the following pins, clock (C), set/reset (SR), 3-state (T), 3-state clock enable (TCE), output (O), output clock enable (OCE). In addition, the output (O) pins must be inverted with respect to each other, and if output registers are used, the INIT states must be opposite values (one High and one Low). If 3-state registers are used, they must be initialized to the same state. Failure to follow these rules leads to DRC errors in the software. VHDL Instantiation data0_p: OBUFT_LVDS port map (I=>data_int(0), T=>data_tri, O=>data_p(0)); data0_inv: INV port map (I=>data_int(0), O=>data_n_int(0)); data0_n: OBUFT_LVDS port map (I=>data_n_int(0), T=>data_tri, O=>data_n(0)); Verilog Instantiation OBUFT_LVDS data0_p (.I(data_int[0]), .T(data_tri), .O(data_p[0])); INV data0_inv (.I(data_int[0], .O(data_n_int[0]); OBUFT_LVDS data0_n (.I(data_n_int[0]), .T(data_tri), .O(data_n[0]));
Adding Output and 3-State Registers
All LVDS buffers can have an output register in the IOB. The output registers must be in both the P-side and N-side IOBs. All the normal IOB register options are available (FD, FDE, FDC, FDCE, FDP, FDPE, FDR, FDRE, FDS, FDSE, LD, LDE, LDC, LDCE, LDP, LDPE). The register elements can be inferred or explicitly instantiated in the HDL code. Special care must be taken to insure that the D pins of the registers are inverted and that the INIT states of the registers are opposite. The 3-state (T), 3-state clock enable (CE), clock pin (C), output clock enable (CE) and set/reset (CLR/PRE or S/R) pins must connect to the same source. Failure to do this leads to a DRC error in the software. The register elements can be packed in the IOB using the IOB property to TRUE on the register or by using the "map -pr [i|o|b]" where "i" is inputs only, "o" is outputs only and "b" is both inputs and outputs. To improve design coding times VHDL and Verilog synthesis macro libraries have been developed to explicitly create these structures. The input library macros are listed below. The 3-state is configured to be 3-stated at GSR and when the PRE,CLR,S or R is asserted and shares it's clock enable with the output register. If this is not desirable, the library can be updated by the user for the desired functionality. The O and OB inputs to the macros are the external net connections.
Creating LVDS Bidirectional Buffer
LVDS bidirectional buffers can be placed in a wide number of IOB locations. The exact locations are dependent on the package used. The Virtex-E package information lists the possible locations as IO_L#P for the P-side and IO_L#N for the N-side, where # is the pair number.
Location Constraints
All LVDS buffers must be explicitly placed on a device. For the output buffers this can be done with the following constraint in the UCF or NCF file. NET data_p<0> LOC = D28; # IO_L0P NET data_n<0> LOC = B29; # IO_L0N
HDL Instantiation
Both bidirectional buffers are required to be instantiated in the design and placed on the correct IO_L#P and IO_L#N locations. The IOB must have the same net source the following pins, clock (C), set/reset (SR), 3-state (T), 3-state clock enable (TCE), output (O), output clock enable (OCE). In addition, the output (O) pins must be inverted with respect to each other, and if output registers are used, the INIT states must be opposite values (one HIGH and one LOW). If 3-state registers are used, they must be initialized to the same state. Failure to follow these rules leads to DRC errors in the software.
Synchronous vs. Asynchronous 3-State Outputs
If the outputs are synchronous (registered in the IOB), then any IO_L#P|N pair can be used. If the outputs are asynchronous (no output register), then they must use one of the pairs that are part of the same IOB group at the end of a ROW or at the top/bottom of a COLUMN in the device. This applies for either the 3-state pin or the data out pin.
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VirtexTM-E 1.8 V Extended Memory Field Programmable Gate Arrays The LVDS pairs that can be used as asynchronous bidirectional buffers are listed in the Virtex-E pinout tables. Some pairs are marked as asynchronous capable for all devices in that package, and others are marked as available only for that device in the package. If the device size might change at some point in the product's lifetime, then only the common pairs for all packages should be used.
VHDL Instantiation data0_p: IOBUF_LVDS port map (I=>data_out(0), T=>data_tri, IO=>data_p(0), O=>data_int(0)); data0_inv: INV (I=>data_out(0), port map O=>data_n_out(0));
data0_n : IOBUF_LVDS port map (I=>data_n_out(0), T=>data_tri, IO=>data_n(0), O=>open); Verilog Instantiation IOBUF_LVDS data0_p(.I(data_out[0]), .T(data_tri), .IO(data_p[0]), .O(data_int[0]); INV data0_inv (.I(data_out[0], .O(data_n_out[0]); IOBUF_LVDS data0_n(.I(data_n_out[0]),.T(data_tri),. IO(data_n[0]).O());
Adding Output and 3-State Registers
All LVDS buffers can have output and input registers in the IOB. The output registers must be in both the P-side and N-side IOBs, the input register is only in the P-side. All the normal IOB register options are available (FD, FDE, FDC, FDCE, FDP, FDPE, FDR, FDRE, FDS, FDSE, LD, LDE, LDC, LDCE, LDP, LDPE). The register elements can be inferred or explicitly instantiated in the HDL code. Special care must be taken to insure that the D pins of the registers are inverted and that the INIT states of the registers are opposite. The 3-state (T), 3-state clock enable (CE), clock pin (C), output clock enable (CE), and set/reset (CLR/PRE or S/R) pins must connect to the same source. Failure to do this leads to a DRC error in the software. The register elements can be packed in the IOB using the IOB property to TRUE on the register or by using the "map -pr [i|o|b]", where "i" is inputs only, "o" is outputs only, and "b" is both inputs and outputs. To improve design coding times, VHDL and Verilog synthesis macro libraries have been developed to explicitly create these structures. The bidirectional I/O library macros are listed in Table 44. The 3-state is configured to be 3-stated at GSR and when the PRE, CLR, S, or R is asserted and shares its clock enable with the output and input register. If this is not desirable, then the library can be updated with the desired functionality by the user. The I/O and IOB inputs to the macros are the external net connections.
Location Constraints
All LVDS buffers must be explicitly placed on a device. For the output buffers this can be done with the following constraint in the UCF or NCF file. NET data_p<0> LOC = D28; # IO_L0P NET data_n<0> LOC = B29; # IO_L0N
Synchronous vs. Asynchronous Bidirectional Buffers
If the output side of the bidirectional buffers are synchronous (registered in the IOB), then any IO_L#P|N pair can be used. If the output side of the bidirectional buffers are asynchronous (no output register), then they must use one of the pairs that is a part of the asynchronous LVDS IOB group. This applies for either the 3-state pin or the data out pin. Table 44: Bidirectional I/O Library Macros Name IOBUFDS_FD_LVDS IOBUFDS_FDE_LVDS IOBUFDS_FDC_LVDS IOBUFDS_FDCE_LVDS IOBUFDS_FDP_LVDS IOBUFDS_FDPE_LVDS IOBUFDS_FDR_LVDS IOBUFDS_FDRE_LVDS IOBUFDS_FDS_LVDS IOBUFDS_FDSE_LVDS
Inputs D, T, C D, T, CE, C D, T, C, CLR D, T, CE, C, CLR D, T, C, PRE D, T, CE, C, PRE D, T, C, R D, T, CE, C, R D, T, C, S D, T, CE, C, S
Bidirectional IO, IOB IO, IOB IO, IOB IO, IOB IO, IOB IO, IOB IO, IOB IO, IOB IO, IOB IO, IOB
Outputs Q Q Q Q Q Q Q Q Q Q
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VirtexTM-E 1.8 V Extended Memory Field Programmable Gate Arrays Table 44: Bidirectional I/O Library Macros (Continued) Name IOBUFDS_LD_LVDS IOBUFDS_LDE_LVDS IOBUFDS_LDC_LVDS IOBUFDS_LDCE_LVDS IOBUFDS_LDP_LVDS IOBUFDS_LDPE_LVDS Inputs D, T, G D, T, GE, G D, T, G, CLR D, T, GE, G, CLR D, T, G, PRE D, T, GE, G, PRE Bidirectional IO, IOB IO, IOB IO, IOB IO, IOB IO, IOB IO, IOB Outputs Q Q Q Q Q Q
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Revision History
The following table shows the revision history for this document. Date 03/23/00 08/01/00 Version 1.0 1.1 Initial Xilinx release. Accumulated edits and fixes. Upgrade to Preliminary. Preview -8 numbers added. Reformatted to adhere to corporate documentation style guidelines. Minor changes in BG560 pin-out table. * * * * * * * 04/02/01 1.4 * * * * * * * In Table 3 (Module 4), FG676 Fine-Pitch BGA -- XCV405E, the following pins are no longer labeled as VREF: B7, G16, G26, W26, AF20, AF8, Y1, H1. Min values added to Virtex-E Electrical Characteristics tables. Updated speed grade -8 numbers in Virtex-E Electrical Characteristics tables (Module 3). Updated minimums in Table 11 (Module 2), and added notes to Table 12 (Module 2). Added to note 2 of Absolute Maximum Ratings (Module 3). Changed all minimum hold times to -0.4 for Global Clock Set-Up and Hold for LVTTL Standard, with DLL (Module 3). Revised maximum TDLLPW in -6 speed grade for DLL Timing Parameters (Module 3). In Table 4, FG676 Fine-Pitch BGA -- XCV405E, pin B19 is no longer labeled as VREF, and pin G16 is now labeled as VREF. Updated values in Virtex-E Switching Characteristics tables. Converted data sheet to modularized format. Modified Figure 30, which shows "DLL Generation of 4x Clock in Virtex-E Devices." Made minor edits to text under Configuration. Added warning under Configuration section that attempting to load an incorrect bitstream causes configuration to fail and can damage the device. Data sheet designation upgraded from Preliminary to Production. Revision
09/19/00
1.2
11/20/00
1.3
04/19/01 07/23/01 11/16/01 07/17/02
1.5 1.6 2.0 2.1
Virtex-E Extended Memory Data Sheet
The Virtex-E Extended Memory Data Sheet contains the following modules: * * DS025-1, Virtex-E 1.8V Extended Memory FPGAs:
Introduction and Ordering Information (Module 1)
* *
DS025-3, Virtex-E 1.8V Extended Memory FPGAs:
DC and Switching Characteristics (Module 3)
DS025-2, Virtex-E 1.8V Extended Memory FPGAs:
Functional Description (Module 2)
DS025-4, Virtex-E 1.8V Extended Memory FPGAs:
Pinout Tables (Module 4)
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Production Product Specification
Virtex-E Extended Memory Electrical Characteristics
Definition of Terms
Electrical and switching characteristics are specified on a per-speed-grade basis and can be designated as Advance, Preliminary, or Production. Each designation is defined as follows: Advance: These speed files are based on simulations only and are typically available soon after device design specifications are frozen. Although speed grades with this designation are considered relatively stable and conservative, some under-reporting might still occur. Preliminary: These speed files are based on complete ES (engineering sample) silicon characterization. Devices and speed grades with this designation are intended to give a better indication of the expected performance of production silicon. The probability of under-reporting delays is greatly reduced as compared to Advance data. Production: These speed files are released once enough production silicon of a particular device family member has been characterized to provide full correlation between speed files and devices over numerous production lots. There is no under-reporting of delays, and customers receive formal notification of any subsequent changes. Typically, the slowest speed grades transition to Production before faster speed grades. All specifications are representative of worst-case supply voltage and junction temperature conditions. The parameters included are common to popular designs and typical applications. Contact the factory for design considerations requiring more detailed information. Table 1 correlates the current status of each Virtex-E Extended Memory device with a corresponding speed file designation. Table 1: Virtex-E Extended Memory Device Speed Grade Designations Speed Grade Designations Device
XCV405E XCV812E
Advance
Preliminary
Production
-8, -7, -6 -8, -7, -6
All specifications are subject to change without notice.
DC Characteristics
Absolute Maximum Ratings
Symbol VCCINT VCCO VREF VIN VTS VCC TSTG TJ Description(1) Internal Supply voltage relative to GND (2) Supply voltage relative to GND Input Reference Voltage Input voltage relative to GND Voltage applied to 3-state output Longest Supply Voltage Rise Time from 0 V - 1.71 V Storage temperature (ambient) Junction temperature (3) Plastic packages -0.5 to 2.0 -0.5 to 4.0 -0.5 to 4.0 -0.5 to 4.0 -0.5 to 4.0 50 -65 to +150 +125 Units V V V V V ms C C
Notes: 1. Stresses beyond those listed under Absolute Maximum Ratings can cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time can affect device reliability. 2. For soldering guidelines and thermal considerations, see the Device Packaging information on the Xilinx website.
(c) 2000-2002 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm. All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
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Recommended Operating Conditions
Symbol VCCINT Description Internal Supply voltage relative to GND, TJ = 0 C to +85C Internal Supply voltage relative to GND, TJ = -40C to +100C VCCO Supply voltage relative to GND, TJ = 0 C to +85C Supply voltage relative to GND, TJ = -40C to +100C TIN Input signal transition time Commercial Industrial Commercial Industrial Min 1.8 - 5% 1.8 - 5% 1.2 1.2 Max 1.8 + 5% 1.8 + 5% 3.6 3.6 250 Units V V V V ns
DC Characteristics Over Recommended Operating Conditions
Symbol VDRINT VDRIO ICCINTQ Description(1) Data Retention VCCINT Voltage (below which configuration data might be lost) Data Retention VCCO Voltage (below which configuration data might be lost) Quiescent VCCINT supply current1 Quiescent VCCO supply current1 Input or output leakage current Input capacitance (sample tested) BGA, PQ, HQ, packages Device All Min 1.5 Max Units V
All XCV405E XCV812E XCV405E XCV812E All All All
1.2 400 500 2 2 -10 +10 8 Note 2 Note 2 0.25 0.25
V mA mA mA mA A pF mA mA
ICCOQ IL CIN IRPU IRPD
Pad pull-up (when selected) @ Vin = 0 V, VCCO = 3.3 V (sample tested) Pad pull-down (when selected) @ Vin = 3.6 V (sample tested)
Notes: 1. With no output current loads, no active input pull-up resistors, all I/O pins 3-stated and floating. 2. Internal pull-up and pull-down resistors guarantee valid logic levels at unconnected input pins. These pull-up and pull-down resistors do not guarantee valid logic levels when input pins are connected to other circuits.
Power-On Power Supply Requirements
Xilinx FPGAs require a certain amount of supply current during power-on to insure proper device operation. The actual current consumed depends on the power-on ramp rate of the power supply. This is the time required to reach the nominal power supply voltage of the device 1 from 0 V. The fastest suggested ramp rate is 0 V to nominal voltage in 2 ms and the slowest allowed ramp rate is 0 V to nominal voltage in 50 ms. For more details on power supply requirements, see xapp158. Product (Commercial Grade) XCV50E - XCV600E XCV812E - XCV2000E XCV2600E - XCV3200E Virtex-E Family, Industrial Grade Description(2) Minimum required current supply Minimum required current supply Minimum required current supply Minimum required current supply Current Requirement(3) 500 mA 1A 1.2 A 2A
Notes: 1. Ramp rate used for this specification is from 0 - 1.8 V DC. Peak current occurs on or near the internal power-on reset threshold and lasts for less than 3 ms. 2. Devices are guaranteed to initialize properly with the minimum current available from the power supply as noted above. 3. Larger currents might result if ramp rates are forced to be faster.
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VirtexTM-E 1.8 V Extended Memory Field Programmable Gate Arrays
DC Input and Output Levels
Values for VIL and VIH are recommended input voltages. Values for IOL and IOH are guaranteed over the recommended operating conditions at the VOL and VOH test points. Only selected standards are tested. These are chosen to ensure that all standards meet their specifications. The selected standards are tested at minimum VCCO with the respective VOL and VOH voltage levels shown. Other standards are sample tested. Input/Output Standard LVTTL(1) LVCMOS2 LVCMOS18 PCI, 3.3 V GTL GTL+ HSTL I(3) HSTL III HSTL IV SSTL3 I SSTL3 II SSTL2 I SSTL2 II CTT AGP V, min - 0.5 - 0.5 - 0.5 - 0.5 - 0.5 - 0.5 - 0.5 - 0.5 - 0.5 - 0.5 - 0.5 - 0.5 - 0.5 - 0.5 - 0.5 VIL V, max 0.8 0.7 20% VCCO 30% VCCO VREF - 0.05 VREF - 0.1 VREF - 0.1 VREF - 0.1 VREF - 0.1 VREF - 0.2 VREF - 0.2 VREF - 0.2 VREF - 0.2 VREF - 0.2 VREF - 0.2 V, min 2.0 1.7 70% VCCO 50% VCCO VREF + 0.05 VREF + 0.1 VREF + 0.1 VREF + 0.1 VREF + 0.1 VREF + 0.2 VREF + 0.2 VREF + 0.2 VREF + 0.2 VREF + 0.2 VREF + 0.2 VIH V, max 3.6 2.7 1.95 VCCO + 0.5 3.6 3.6 3.6 3.6 3.6 3.6 3.6 3.6 3.6 3.6 3.6 VOL V, Max 0.4 0.4 0.4 10% VCCO 0.4 0.6 0.4 0.4 0.4 VREF - 0.6 VREF - 0.8 VREF - 0.61 VREF - 0.80 VREF - 0.4 10% VCCO VOH V, Min 2.4 1.9 VCCO - 0.4 90% VCCO n/a n/a VCCO - 0.4 VCCO - 0.4 VCCO - 0.4 VREF + 0.6 VREF + 0.8 VREF + 0.61 VREF + 0.80 VREF + 0.4 90% VCCO IOL mA 24 12 8 Note 2 40 36 8 24 48 8 16 7.6 15.2 8 Note 2 IOH mA - 24 - 12 -8 Note 2 n/a n/a -8 -8 -8 -8 -16 -7.6 -15.2 -8 Note 2
Notes: 1. VOL and VOH for lower drive currents are sample tested. 2. Tested according to the relevant specifications. 3. DC input and output levels for HSTL18 (HSTL I/O standard with VCCO of 1.8 V) are provided in an HSTL white paper on the Xilinx website.
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LVDS DC Specifications
DC Parameter Supply Voltage Output High Voltage for Q and Q Output Low Voltage for Q and Q Differential Output Voltage (Q - Q), Q = High (Q - Q), Q = High Output Common-Mode Voltage Differential Input Voltage (Q - Q), Q = High (Q - Q), Q = High Input Common-Mode Voltage VICM Differential input voltage = 350 mV 0.2 1.25 2.2 V VOCM VIDIFF RT = 100 across Q and Q signals Common-mode input voltage = 1.25 V 1.125 100 1.25 350 1.375 NA V mV Symbol VCCO VOH VOL VODIFF RT = 100 across Q and Q signals RT = 100 across Q and Q signals RT = 100 across Q and Q signals Conditions Min 2.375 1.25 0.9 250 Typ 2.5 1.425 1.075 350 Max 2.625 1.6 1.25 450 Units V V V mV
Notes: 1. Refer to the Design Consideration section for termination schematics.
LVPECL DC Specifications
These values are valid at the output of the source termination pack shown under LVPECL, with a 100 differential load only. The VOH levels are 200 mV below standard LVPECL levels and are compatible with devices tolerant of lower common-mode ranges. The following table summarizes the DC output specifications of LVPECL. DC Parameter VCCO VOH VOL VIH VIL
Differential Input Voltage
Min 3.0 1.8 0.96 1.49 0.86 0.3
Max
Min 3.3
Max
Min 3.6
Max
Units V
2.11 1.27 2.72 2.125 -
1.92 1.06 1.49 0.86 0.3
2.28 1.43 2.72 2.125 -
2.13 1.30 1.49 0.86 0.3
2.41 1.57 2.72 2.125 -
V V V V V
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VirtexTM-E 1.8 V Extended Memory Field Programmable Gate Arrays
Virtex-E Switching Characteristics
All devices are 100% functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are representative values. For more specific, more precise, and worst-case guaranteed data, use the values reported by the static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation net list. All timing parameters assume worst-case operating conditions (supply voltage and junction temperature). Values apply to all Virtex-E devices unless otherwise noted.
IOB Input Switching Characteristics
Input delays associated with the pad are specified for LVTTL levels. For other standards, adjust the delays with the values shown in ``IOB Input Switching Characteristics Standard Adjustments'' on page 6. Speed Grade(2) Description(1)
Propagation Delays
Symbol
Device
Min
-8
-7
-6
Units
Pad to I output, no delay Pad to I output, with delay
Propagation Delays
TIOPI TIOPID
All XCV405E XCV812E
0.43 0.51 0.55
0.8 1.0 1.1
0.8 1.0 1.1
0.8 1.0 1.1
ns, max ns, max ns, max
Pad to output IQ via transparent latch, no delay Pad to output IQ via transparent latch, with delay Clock CLK to output IQ
TIOPLI TIOPLID TIOCKIQ TIOPICK / TIOICKP TIOPICKD / TIOICKPD TIOICECK / TIOCKICE TIOSRCKI
All XCV405E XCV812E All
0.75 1.55 1.55 0.18
1.4 3.5 3.5 0.4
1.5 3.6 3.6 0.7
1.6 3.7 3.7 0.7
ns, max ns, max ns, max ns, max
Setup and Hold Times with respect to Clock at IOB Input Register
Pad, no delay
All XCV405E XCV812E All All
0.69 / 0 1.49 / 0 1.49 / 0 0.28 / 0.0 0.38
1.3 / 0 3.4 / 0 3.4 / 0 0.55 / 0.01 0.8
1.4 / 0 3.5 / 0 3.5 / 0 0.7 / 0.01 0.9
1.5 / 0 3.5 / 0 3.5 / 0 0.7 / 0.01 1.0
ns, min ns, min ns, min ns, min ns, min
Pad, with delay ICE input SR input (IFF, synchronous)
Set/Reset Delays
SR input to IQ (asynchronous) GSR to output IQ
TIOSRIQ TGSRQ
All All
0.54 3.88
1.1 7.6
1.2 8.5
1.4 9.7
ns, max ns, max
Notes: 1. A Zero "0" Hold Time listing indicates no hold time or a negative hold time. Negative values can not be guaranteed "best-case", but if a "0" is listed, there is no positive hold time. 2. Input timing i for LVTTL is measured at 1.4 V. For other I/O standards, see Table 3.
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IOB Input Switching Characteristics Standard Adjustments
Speed Grade(1) Description
Data Input Delay Adjustments
Symbol
Standard
Min
-8
-7
-6
Units
Standard-specific data input delay adjustments
TILVTTL TILVCMOS2 TILVCMOS18 TILVDS TILVPECL TIPCI33_3 TIPCI66_3 TIGTL TIGTLPLUS TIHSTL TISSTL2 TISSTL3 TICTT TIAGP
LVTTL LVCMOS2 LVCMOS18 LVDS LVPECL PCI, 33 MHz, 3.3 V PCI, 66 MHz, 3.3 V GTL GTL+ HSTL SSTL2 SSTL3 CTT AGP
0.0 -0.02 -0.02 0.00 0.00 -0.05 -0.05 +0.10 +0.06 +0.02 -0.04 -0.02 +0.01 -0.03
0.0 0.0 +0.20 +0.15 +0.15 +0.08 -0.11 +0.14 +0.14 +0.04 +0.04 +0.04 +0.10 +0.04
0.0 0.0 +0.20 +0.15 +0.15 +0.08 -0.11 +0.14 +0.14 +0.04 +0.04 +0.04 +0.10 +0.04
0.0 0.0 +0.20 +0.15 +0.15 +0.08 -0.11 +0.14 +0.14 +0.04 +0.04 +0.04 +0.10 +0.04
ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Notes: 1. Input timing i for LVTTL is measured at 1.4 V. For other I/O standards, see Table 3.
I
DQ CE Weak Keeper SR
T TCE
O OCE
DQ CE
PAD OBUFT
SR I IQ Q Programmable Delay IBUF Vref SR SR CLK ICE
ds022_02_091300
D CE
Figure 1: Virtex-E Input/Output Block (IOB)
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VirtexTM-E 1.8 V Extended Memory Field Programmable Gate Arrays
IOB Output Switching Characteristics, Figure 1
Output delays terminating at a pad are specified for LVTTL with 12 mA drive and fast slew rate. For other standards, adjust the delays with the values shown in ``IOB Output Switching Characteristics Standard Adjustments'' on page 8.. Speed Grade(2) Description(1)
Propagation Delays
Symbol TIOOP TIOOLP TIOTHZ TIOTON TIOTLPHZ TIOTLPON TGTS TIOCKP TIOCKHZ TIOCKON TIOOCK / TIOCKO TIOOCECK / TIOCKOCE TIOSRCKO / TIOCKOSR TIOTCK / TIOCKT TIOTCECK / TIOCKTCE TIOSRCKT / TIOCKTSR TIOSRP TIOSRHZ TIOSRON TIOGSRQ
Min3 1.04 1.24 0.73 1.13 0.86 1.26 1.94 0.97 0.77 1.17
-8 2.5 2.9 1.5 2.7 1.8 3.0 4.1 2.4 1.6 2.8
-7 2.7 3.1 1.7 2.9 2.0 3.2 4.6 2.8 2.0 3.2
-6 2.9 3.4 1.9 3.1 2.2 3.4 4.9 2.9 2.2 3.4
Units ns, max ns, max ns, max ns, max ns, max ns, max ns, max ns, max ns, max ns, max
O input to Pad O input to Pad via transparent latch
3-State Delays
T input to Pad high-impedance (Note 2) T input to valid data on Pad T input to Pad high-impedance via transparent latch (Note 2) T input to valid data on Pad via transparent latch GTS to Pad high impedance (Note 2)
Sequential Delays
Clock CLK to Pad Clock CLK to Pad high-impedance (synchronous) (Note 2) Clock CLK to valid data on Pad (synchronous)
Setup and Hold Times before/after Clock CLK
O input OCE input SR input (OFF)
3-State Setup Times, T input 3-State Setup Times, TCE input 3-State Setup Times, SR input (TFF) Set/Reset Delays
0.43 / 0 0.28 / 0 0.40 / 0 0.26 / 0 0.30 / 0 0.38 / 0
0.9 / 0 0.55 / 0.01 0.8 / 0 0.51 / 0 0.6 / 0 0.8 / 0
1.0 / 0 0.7 / 0 0.9 / 0 0.6 / 0 0.7 / 0 0.9 / 0
1.1 / 0 0.7 / 0 1.0 / 0 0.7 / 0 0.8 / 0 1.0 / 0
ns, min ns, min ns, min ns, min ns, min ns, min
SR input to Pad (asynchronous) SR input to Pad high-impedance (asynchronous) (Note 2) SR input to valid data on Pad (asynchronous) GSR to Pad
1.30 1.08 1.48 3.88
3.1 2.2 3.4 7.6
3.3 2.4 3.7 8.5
3.5 2.7 3.9 9.7
ns, max ns, max ns, max ns, max
Notes: 1. A Zero "0" Hold Time listing indicates no hold time or a negative hold time. Negative values can not be guaranteed "best-case", but if a "0" is listed, there is no positive hold time. 2. 3-state turn-off delays should not be adjusted.
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IOB Output Switching Characteristics Standard Adjustments
Output delays terminating at a pad are specified for LVTTL with 12 mA drive and fast slew rate. For other standards, adjust the delays by the values shown. Speed Grade Description
Output Delay Adjustments
Symbol
Standard
Min
-8
-7
-6
Units
Standard-specific adjustments for output delays terminating at pads (based on standard capacitive load, Csl)
TOLVTTL_S2 TOLVTTL_S4 TOLVTTL_S6 TOLVTTL_S8 TOLVTTL_S12 TOLVTTL_S16 TOLVTTL_S24 TOLVTTL_F2 TOLVTTL_F4 TOLVTTL_F6 TOLVTTL_F8 TOLVTTL_F12 TOLVTTL_F16 TOLVTTL_F24 TOLVCMOS_2 TOLVCMOS_18 TOLVDS TOLVPECL TOPCI33_3 TOPCI66_3 TOGTL TOGTLP TOHSTL_I TOHSTL_IIII TOHSTL_IV TOSSTL2_I TOSSTL2_II TOSSTL3_I TOSSTL3_II TOCTT TOAGP
LVTTL, Slow, 2 mA 4 mA 6 mA 8 mA 12 mA 16 mA 24 mA LVTTL, Fast, 2 mA 4 mA 6 mA 8 mA 12 mA 16 mA 24 mA LVCMOS2 LVCMOS18 LVDS LVPECL PCI, 33 MHz, 3.3 V PCI, 66 MHz, 3.3 V GTL GTL+ HSTL I HSTL III HSTL IV SSTL2 I SSTL2 II SSTL3 I SSTL3 II CTT AGP
4.2 2.5 1.8 1.2 1.0 0.9 0.8 1.9 0.7 0.20 0.10 0.0 -0.10 -0.10 0.10 0.10 -0.39 -0.20 0.50 0.10 0.6 0.7 0.10 -0.10 -0.20 -0.10 -0.20 -0.20 -0.30 0.0 -0.1
+14.7 +7.5 +4.8 +3.0 +1.9 +1.7 +1.3 +13.1 +5.3 +3.1 +1.0 0.0 -0.05 -0.20 +0.09 +0.7 -1.2 -0.41 +2.3 -0.41 +0.49 +0.8 -0.51 -0.91 -1.01 -0.51 -0.91 -0.51 -1.01 -0.61 -0.91
+14.7 +7.5 +4.8 +3.0 +1.9 +1.7 +1.3 +13.1 +5.3 +3.1 +1.0 0.0 -0.05 -0.20 +0.09 +0.7 -1.2 -0.41 +2.3 -0.41 +0.49 +0.8 -0.51 -0.91 -1.01 -0.51 -0.91 -0.51 -1.01 -0.61 -0.91
+14.7 +7.5 +4.8 +3.0 +1.9 +1.7 +1.3 +13.1 +5.3 +3.1 +1.0 0.0 -0.05 -0.20 +0.09 +0.7 -1.2 -0.41 +2.3 -0.41 +0.49 +0.8 -0.51 -0.91 -1.01 -0.51 -0.91 -0.51 -1.01 -0.61 -0.91
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
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VirtexTM-E 1.8 V Extended Memory Field Programmable Gate Arrays
Calculation of Tioop as a Function of Capacitance
Tioop is the propagation delay from the O Input of the IOB to the pad. The values for Tioop are based on the standard capacitive load (Csl) for each I/O standard as listed in Table 2. Table 2: Constants for Use in Calculation of Tioop Standard LVTTL Fast Slew Rate, 2mA drive LVTTL Fast Slew Rate, 4mA drive LVTTL Fast Slew Rate, 6mA drive LVTTL Fast Slew Rate, 8mA drive LVTTL Fast Slew Rate, 12mA drive LVTTL Fast Slew Rate, 16mA drive LVTTL Fast Slew Rate, 24mA drive LVTTL Slow Slew Rate, 2mA drive LVTTL Slow Slew Rate, 4mA drive LVTTL Slow Slew Rate, 6mA drive LVTTL Slow Slew Rate, 8mA drive LVTTL Slow Slew Rate, 12mA drive LVTTL Slow Slew Rate, 16mA drive LVTTL Slow Slew Rate, 24mA drive LVCMOS2 LVCMOS18 PCI 33 MHZ 3.3 V PCI 66 MHz 3.3 V GTL GTL+ HSTL Class I HSTL Class III HSTL Class IV SSTL2 Class I SSTL2 Class II SSTL3 Class I SSTL3 Class II CTT AGP Csl (pF) 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 10 10 0 0 20 20 20 30 30 30 30 20 10 fl (ns/pF) 0.41 0.20 0.13 0.079 0.044 0.043 0.033 0.41 0.20 0.10 0.086 0.058 0.050 0.048 0.041 0.050 0.050 0.033 0.014 0.017 0.022 0.016 0.014 0.028 0.016 0.029 0.016 0.035 0.037
LVDS LVPECL AGP GTL GTL+ HSTL Class I HSTL Class III HSTL Class IV SSTL3 I & II SSTL2 I & II CTT VREF -0.2 VREF -0.2 VREF -0.5 VREF -0.5 VREF -0.5 VREF -1.0 VREF -0.75 VREF -0.2 VREF - (0.2xVCCO) 1.2 - 0.125 1.6 - 0.3 VREF +0.2 VREF +0.2 VREF +0.5 VREF +0.5 VREF +0.5 VREF +1.0 VREF +0.75 VREF +0.2 VREF + (0.2xVCCO) 1.2 + 0.125 1.6 + 0.3 VREF VREF VREF VREF VREF VREF VREF VREF 0.80 1.0 0.75 0.90 0.90 1.5 1.25 1.5 Per AGP Spec Standard LVTTL LVCMOS2 PCI33_3 PCI66_3 VL1 0 0 VH1 3 2.5 Per PCI Spec Per PCI Spec
For other capacitive loads, use the formulas below to calculate the corresponding Tioop. Tioop = Tioop + Topadjust + (Cload - Csl) * fl where: Topadjust is reported above in the Output Delay Adjustment section. Cload is the capacitive load for the design. Table 3: Delay Measurement Methodology
Meas. Point 1.4 1.125 VREF (Typ)2 -
VREF 1.2 1.6
Notes: 1. Input waveform switches between VLand VH. 2. Measurements are made at VREF (Typ), Maximum, and Minimum. Worst-case values are reported. I/O parameter measurements are made with the capacitance values shown in Table 2. See the Application Examples for appropriate terminations. I/O standard measurements are reflected in the IBIS model information except where the IBIS format precludes it.
Notes: 1. I/O parameter measurements are made with the capacitance values shown above. See the Application Examples for appropriate terminations. 2. I/O standard measurements are reflected in the IBIS model information except where the IBIS format precludes it.
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Clock Distribution Switching Characteristics
Speed Grade Description
GCLK IOB and Buffer
Symbol
Min
-8
-7
-6
Units
Global Clock PAD to output. Global Clock Buffer I input to O output
TGPIO TGIO
0.38 0.11
0.7 0.19
0.7 0.45
0.7 0.50
ns, max ns, max
I/O Standard Global Clock Input Adjustments
Speed Grade Description(1)
Data Input Delay Adjustments
Symbol
Standard
Min
-8
-7
-6
Units
Standard-specific global clock input delay adjustments
TGPLVTTL TGPLVCMOS2 TGPLVCMOS18 TGLVDS TGLVPECL TGPPCI33_3 TGPPCI66_3 TGPGTL TGPGTLP TGPHSTL TGPSSTL2 TGPSSTL3 TGPCTT TGPAGP
LVTTL LVCMOS2 LVCMOS2 LVDS LVPECL PCI, 33 MHz, 3.3 V PCI, 66 MHz, 3.3 V GTL GTL+ HSTL SSTL2 SSTL3 CTT AGP
0.0 -0.02 0.12 0.23 0.23 -0.05 -0.05 0.20 0.20 0.18 0.21 0.18 0.22 0.21
0.0 0.0 0.20 0.38 0.38 0.08 -0.11 0.37 0.37 0.27 0.27 0.27 0.33 0.27
0.0 0.0 0.20 0.38 0.38 0.08 -0.11 0.37 0.37 0.27 0.27 0.27 0.33 0.27
0.0 0.0 0.20 0.38 0.38 0.08 -0.11 0.37 0.37 0.27 0.27 0.27 0.33 0.27
ns, max ns, max ns, max ns, max ns, max ns, max ns, max ns, max ns, max ns, max ns, max ns, max ns, max ns, max
Notes: 1. Input timing for GPLVTTL is measured at 1.4 V. For other I/O standards, see Table 3.
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VirtexTM-E 1.8 V Extended Memory Field Programmable Gate Arrays
CLB Switching Characteristics
Delays originating at F/G inputs vary slightly according to the input used, see Figure 2. The values listed below are worst-case. Precise values are provided by the timing analyzer. Speed Grade Description(1)
Combinatorial Delays
Symbol TILO TIF5 TIF5X TIF6Y TF5INY TIFNCTL TBYYB TCKO TCKLO TICK / TCKI TIF5CK / TCKIF5 TF5INCK / TCKF5IN TIF6CK / TCKIF6 TDICK / TCKDI TCECK / TCKCE TRCK / TCKR TCH TCL TRPW TRQ FTOG
Min
-8
-7
-6
Units ns, max ns, max ns, max ns, max ns, max ns, max ns, max ns, max ns, max
4-input function: F/G inputs to X/Y outputs 5-input function: F/G inputs to F5 output 5-input function: F/G inputs to X output 6-input function: F/G inputs to Y output via F6 MUX 6-input function: F5IN input to Y output Incremental delay routing through transparent latch to XQ/YQ outputs BY input to YB output
Sequential Delays
0.19 0.36 0.35 0.35 0.04 0.27 0.19
0.40 0.76 0.74 0.74 0.11 0.63 0.38
0.42 0.8 0.8 0.9 0.20 0.7 0.46
0.47 0.9 0.9 1.0 0.22 0.8 0.51
FF Clock CLK to XQ/YQ outputs Latch Clock CLK to XQ/YQ outputs
Setup and Hold Times before/after Clock CLK
0.34 0.40
0.78 0.77
0.9 0.9
1.0 1.0
4-input function: F/G Inputs 5-input function: F/G inputs 6-input function: F5IN input 6-input function: F/G inputs via F6 MUX BX/BY inputs CE input SR/BY inputs (synchronous)
Clock CLK
0.39 / 0 0.55 / 0 0.27 / 0 0.58 / 0 0.25 / 0 0.28 / 0 0.24 / 0
0.9 / 0 1.3 / 0 0.6 / 0 1.3 / 0 0.6 / 0 0.55 / 0 0.46 / 0
1.0 / 0 1.4 / 0 0.8 / 0 1.5 / 0 0.7 / 0 0.7 / 0 0.52 / 0
1.1 / 0 1.5 / 0 0.8 / 0 1.6 / 0 0.8 / 0 0.7 / 0 0.6 / 0
ns, min ns, min ns, min ns, min ns, min ns, min ns, min
Minimum Pulse Width, High Minimum Pulse Width, Low
Set/Reset
0.56 0.56
1.2 1.2
1.3 1.3
1.4 1.4
ns, min ns, min ns, min ns, max MHz
Minimum Pulse Width, SR/BY inputs Delay from SR/BY inputs to XQ/YQ outputs (asynchronous) Toggle Frequency (MHz) (for export control)
0.94 0.39 -
1.9 0.8 416
2.1 0.9 400
2.4 1.0 357
Notes: 1. A Zero "0" Hold Time listing indicates no hold time or a negative hold time. Negative values can not be guaranteed "best-case", but if a "0" is listed, there is no positive hold time.
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COUT
YB CY G4 G3 G2 G1 I3 I2 I1 I0 LUT WE O DI INIT DQ CE REV XB F5IN F6 CY CK WE A4 BX F4 F3 F2 F1 I3 I2 I1 I0 WE LUT 0 1 SR CLK CE DI O REV WSO WSH BY DG BX DI INIT DQ CE F5 F5 X XQ Y YQ
0 1
BY
CIN
ds022_05_092000
Figure 2: Detailed View of Virtex-E Slice
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VirtexTM-E 1.8 V Extended Memory Field Programmable Gate Arrays
CLB Arithmetic Switching Characteristics
Setup times not listed explicitly can be approximated by decreasing the combinatorial delays by the setup time adjustment listed. Precise values are provided by the timing analyzer. Speed Grade Description(1)
Combinatorial Delays
Symbol
Min
-8
-7
-6
Units
F operand inputs to X via XOR F operand input to XB output F operand input to Y via XOR F operand input to YB output F operand input to COUT output G operand inputs to Y via XOR G operand input to YB output G operand input to COUT output BX initialization input to COUT CIN input to X output via XOR CIN input to XB CIN input to Y via XOR CIN input to YB CIN input to COUT output
Multiplier Operation
TOPX TOPXB TOPY TOPYB TOPCYF TOPGY TOPGYB TOPCYG TBXCY TCINX TCINXB TCINY TCINYB TBYP
0.32 0.35 0.59 0.48 0.37 0.34 0.47 0.36 0.19 0.27 0.02 0.26 0.16 0.05
0.68 0.65 1.07 0.89 0.71 0.72 0.78 0.60 0.36 0.50 0.04 0.45 0.28 0.10
0.8 0.8 1.4 1.1 0.9 0.8 1.2 0.9 0.51 0.6 0.07 0.7 0.38 0.14
0.8 0.9 1.5 1.3 1.0 0.9 1.3 1.0 0.57 0.7 0.08 0.7 0.43 0.15
ns, max ns, max ns, max ns, max ns, max ns, max ns, max ns, max ns, max ns, max ns, max ns, max ns, max ns, max
F1/2 operand inputs to XB output via AND F1/2 operand inputs to YB output via AND F1/2 operand inputs to COUT output via AND G1/2 operand inputs to YB output via AND G1/2 operand inputs to COUT output via AND
Setup and Hold Times before/after Clock CLK
TFANDXB TFANDYB TFANDCY TGANDYB TGANDCY
0.10 0.28 0.17 0.20 0.09
0.30 0.56 0.38 0.46 0.28
0.35 0.7 0.46 0.55 0.30
0.39 0.8 0.51 0.7 0.34
ns, max ns, max ns, max ns, max ns, max
CIN input to FFX CIN input to FFY
TCCKX/TCKCX TCCKY/TCKCY
0.47 / 0 0.49 / 0
1.0 / 0 0.92 / 0
1.2 / 0 1.2 / 0
1.3 / 0 1.3 / 0
ns, min ns, min
Notes: 1. A Zero "0" Hold Time listing indicates no hold time or a negative hold time. Negative values can not be guaranteed "best-case", but if a "0" is listed, there is no positive hold time.
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CLB Distributed RAM Switching Characteristics
Speed Grade Description(1)
Sequential Delays
Symbol
Min
-8
-7
-6
Units
Clock CLK to X/Y outputs (WE active) 16 x 1 mode Clock CLK to X/Y outputs (WE active) 32 x 1 mode
Shift-Register Mode
TSHCKO16 TSHCKO32
0.67 0.84
1.38 1.66
1.5 1.9
1.7 2.1
ns, max ns, max
Clock CLK to X/Y outputs
Setup and Hold Times before/after Clock CLK
TREG
1.25
2.39
2.9
3.2
ns, max
F/G address inputs BX/BY data inputs (DIN) SR input (WE)
Clock CLK
TAS/TAH TDS/TDH TWS/TWH
0.19 / 0 0.44 / 0 0.29 / 0
0.38 / 0 0.87 / 0 0.57 / 0
0.42 / 0 0.97 / 0 0.7 / 0
0.47 / 0 1.09 / 0 0.8 / 0
ns, min ns, min ns, min
Minimum Pulse Width, High Minimum Pulse Width, Low Minimum clock period to meet address write cycle time
Shift-Register Mode
TWPH TWPL TWC
0.96 0.96 1.92
1.9 1.9 3.8
2.1 2.1 4.2
2.4 2.4 4.8
ns, min ns, min ns, min
Minimum Pulse Width, High Minimum Pulse Width, Low
TSRPH TSRPL
1.0 1.0
1.9 1.9
2.1 2.1
2.4 2.4
ns, min ns, min
Notes: 1. A Zero "0" Hold Time listing indicates no hold time or a negative hold time. Negative values can not be guaranteed "best-case", but if a "0" is listed, there is no positive hold time.
RAMB4_S#_S#
WEA ENA RSTA CLKA ADDRA[#:0] DIA[#:0]
DOA[#:0]
WEB ENB RSTB CLKB ADDRB[#:0] DIB[#:0]
DOB[#:0]
ds022_06_121699
Figure 3: Dual-Port Block SelectRAM
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VirtexTM-E 1.8 V Extended Memory Field Programmable Gate Arrays
Block RAM Switching Characteristics
Speed Grade Description(1)
Sequential Delays
Symbol
Min
-8
-7
-6
Units
Clock CLK to DOUT output
Setup and Hold Times before Clock CLK
TBCKO
0.63
2.46
3.1
3.5
ns, max
ADDR inputs DIN inputs EN input RST input WEN input
Clock CLK
TBACK/TBCKA TBDCK/TBCKD TBECK/TBCKE TBRCK/TBCKR TBWCK/TBCKW
0.42 / 0 0.42 / 0 0.97 / 0 0.9 / 0 0.86 / 0
0.9 / 0 0.9 / 0 2.0 / 0 1.8 / 0 1.7 / 0
1.0 / 0 1.0 / 0 2.2 / 0 2.1 / 0 2.0 / 0
1.1 / 0 1.1 / 0 2.5 / 0 2.3 / 0 2.2 / 0
ns, min ns, min ns, min ns, min ns, min
Minimum Pulse Width, High Minimum Pulse Width, Low CLKA -> CLKB setup time for different ports
TBPWH TBPWL TBCCS
0.6 0.6 1.2
1.2 1.2 2.4
1.35 1.35 2.7
1.5 1.5 3.0
ns, min ns, min ns, min
Notes: 1. A Zero "0" Hold Time listing indicates no hold time or a negative hold time. Negative values can not be guaranteed "best-case", but if a "0" is listed, there is no positive hold time.
TBUF Switching Characteristics
Speed Grade Description
Combinatorial Delays
Symbol
Min
-8
-7
-6
Units
IN input to OUT output TRI input to OUT output high-impedance TRI input to valid data on OUT output
TIO TOFF TON
0.0 0.05 0.05
0.0 0.092 0.092
0.0 0.10 0.10
0 .0 0.11 0.11
ns, max ns, max ns, max
JTAG Test Access Port Switching Characteristics
Description TMS and TDI Setup times before TCK TMS and TDI Hold times after TCK Output delay from clock TCK to output TDO Maximum TCK clock frequency Symbol TTAPTK TTCKTAP TTCKTDO FTCK Value 4.0 2.0 11.0 33 Units ns, min ns, min ns, max MHz, max
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Virtex-E Pin-to-Pin Output Parameter Guidelines
All devices are 100% functionally tested. Listed below are representative values for typical pin locations and normal clock loading. Values are expressed in nanoseconds unless otherwise noted.
Global Clock Input to Output Delay for LVTTL, 12 mA, Fast Slew Rate, with DLL
Speed Grade(2) Description(1) LVTTL Global Clock Input to Output Delay using Output Flip-flop, 12 mA, Fast Slew Rate, with DLL. For data output with different standards, adjust the delays with the values shown in ``IOB Output Switching Characteristics Standard Adjustments'' on page 8.
Notes: 1. Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible IOB and CLB flip-flops are clocked by the global clock net. 2. Output timing is measured at 50% VCC threshold with 35 pF external capacitive load. For other I/O standards and different loads, see Table 2 and Table 3. 3. DLL output jitter is already included in the timing calculation.
Symbol TICKOFDLL
Device(3) XCV405E XCV812E
Min 1.0 1.0
-8 3.1 3.1
-7 3.1 3.1
-6 3.1 3.1
Units ns ns
Global Clock Input to Output Delay for LVTTL, 12 mA, Fast Slew Rate, without DLL
Speed Grade(2) Description(1) LVTTL Global Clock Input to Output Delay using Output Flip-flop, 12 mA, Fast Slew Rate, without DLL. For data output with different standards, adjust the delays with the values shown in ``IOB Output Switching Characteristics Standard Adjustments'' on page 8.
Notes: 1. Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible IOB and CLB flip-flops are clocked by the global clock net. 2. Output timing is measured at 50% VCC threshold with 35 pF external capacitive load. For other I/O standards and different loads, see Table 2 and Table 3.
Symbol TICKOF
Device XCV405E XCV812E
Min 1.6 1.8
-8 4.5 4.8
-7 4.7 5.0
-6 4.9 5.2
Units ns ns
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VirtexTM-E 1.8 V Extended Memory Field Programmable Gate Arrays
Virtex-E Pin-to-Pin Input Parameter Guidelines
All devices are 100% functionally tested. Listed below are representative values for typical pin locations and normal clock loading. Values are expressed in nanoseconds unless otherwise noted.
Global Clock Set-Up and Hold for LVTTL Standard, with DLL
Speed Grade(2) Description(1) Symbol Device(3) Min -8 -7 -6 Units
Input Setup and Hold Time Relative to Global Clock Input Signal for LVTTL Standard. For data input with different standards, adjust the setup time delay by the values shown in ``IOB Input Switching Characteristics Standard Adjustments'' on page 6. No Delay Global Clock and IFF, with DLL TPSDLL/TPHDLL XCV405E XCV812E 1.5 / -0.4 1.5 / -0.4 1.5 / -0.4 1.5 / -0.4 1.6 / -0.4 1.6 / -0.4 1.7 / -0.4 1.7 / -0.4 ns ns
Notes: 1. IFF = Input Flip-Flop or Latch 2. Setup time is measured relative to the Global Clock input signal with the fastest route and the lightest load. Hold time is measured relative to the Global Clock input signal with the slowest route and heaviest load. 3. DLL output jitter is already included in the timing calculation.
Global Clock Set-Up and Hold for LVTTL Standard, without DLL
Speed Grade(2) Description(1) Symbol Device(3) Min -8 -7 -6 Units
Input Setup and Hold Time Relative to Global Clock Input Signal for LVTTL Standard. For data input with different standards, adjust the setup time delay by the values shown in ``IOB Input Switching Characteristics Standard Adjustments'' on page 6. Full Delay Global Clock and IFF, without DLL TPSFD/TPHFD XCV405E XCV812E 2.3 / 0 2.5 / 0 2.3 / 0 2.5 / 0 2.3 / 0 2.5 / 0 2.3 / 0 2.5 / 0 ns ns
Notes: 1. IFF = Input Flip-Flop or Latch 2. Setup time is measured relative to the Global Clock input signal with the fastest route and the lightest load. Hold time is measured relative to the Global Clock input signal with the slowest route and heaviest load. 3. A Zero "0" Hold Time listing indicates no hold time or a negative hold time. Negative values can not be guaranteed "best-case", but if a "0" is listed, there is no positive hold time.
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DLL Timing Parameters
All devices are 100 percent functionally tested. Because of the difficulty in directly measuring many internal timing parameters, those parameters are derived from benchmark timing patterns. The following guidelines reflect worst-case values across the recommended operating conditions. Speed Grade -8 Description Input Clock Frequency (CLKDLLHF) Input Clock Frequency (CLKDLL) Input Clock Low/High Pulse Width Symbol FCLKINHF FCLKINLF TDLLPW 25 MHz 50 MHz 100 MHz 150 MHz 200 MHz 250 MHz 300 MHz FCLKIN Min 60 25 5.0 3.0 2.4 2.0 1.8 1.5 1.3 Max 320 160 Min 60 25 5.0 3.0 2.4 2.0 1.8 1.5 1.3 -7 Max 320 160 Min 60 25 5.0 3.0 2.4 2.0 1.8 1.5 NA -6 Max 260 135 Units MHz MHz ns ns ns ns ns ns ns
Period Tolerance: the allowed input clock period change in nanoseconds.
TCLKIN
TCLKIN + TIPTOL _
Output Jitter: the difference between an ideal reference clock edge and the actual design.
Phase Offset and Maximum Phase Difference
Ideal Period Actual Period +/- Jitter + Maximum Phase Difference + Phase Offset ds022_24_091200 + Jitter
Figure 4: DLL Timing Waveforms
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VirtexTM-E 1.8 V Extended Memory Field Programmable Gate Arrays
DLL Clock Tolerance, Jitter, and Phase Information
All DLL output jitter and phase specifications determined through statistical measurement at the package pins using a clock mirror configuration and matched drivers.
CLKDLLHF Description Input Clock Period Tolerance Input Clock Jitter Tolerance (Cycle to Cycle) Time Required for DLL to Acquire Lock(6) Symbol TIPTOL TIJITCC TLOCK > 60 MHz 50 - 60 MHz 40 - 50 MHz 30 - 40 MHz 25 - 30 MHz Output Jitter (cycle-to-cycle) for any DLL Clock Output(1) Phase Offset between CLKIN and CLKO(2) Phase Offset between Clock Outputs on the DLL(3) Maximum Phase Difference between CLKIN and CLKO(4) Maximum Phase Difference between Clock Outputs on the DLL(5) TOJITCC TPHIO TPHOO TPHIOM TPHOOM FCLKIN Min Max 1.0 150 20 60 100 140 160 200 CLKDLL Min Max 1.0 300 20 25 50 90 120 60 100 140 160 200 Units ns ps s s s s s ps ps ps ps ps
Notes: 1. Output Jitter is cycle-to-cycle jitter measured on the DLL output clock and is based on a maximum tap delay resolution, excluding input clock jitter. 2. Phase Offset between CLKIN and CLKO is the worst-case fixed time difference between rising edges of CLKIN and CLKO, excluding Output Jitter and input clock jitter. 3. Phase Offset between Clock Outputs on the DLL is the worst-case fixed time difference between rising edges of any two DLL outputs, excluding Output Jitter and input clock jitter. 4. Maximum Phase Difference between CLKIN an CLKO is the sum of Output Jitter and Phase Offset between CLKIN and CLKO, or the greatest difference between CLKIN and CLKO rising edges due to DLL alone (excluding input clock jitter). 5. Maximum Phase DIfference between Clock Outputs on the DLL is the sum of Output JItter and Phase Offset between any DLL clock outputs, or the greatest difference between any two DLL output rising edges sue to DLL alone (excluding input clock jitter). 6. Add 30% to the value for Industrial grade parts.
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Revision History
The following table shows the revision history for this document. Date 03/23/00 08/01/00 Version 1.0 1.1 Initial Xilinx release. Accumulated edits and fixes. Upgrade to Preliminary. Preview -8 numbers added. Reformatted to adhere to corporate documentation style guidelines. Minor changes in BG560 pin-out table. * * * * * * * 04/02/01 1.4 * * * 04/19/01 07/23/01 1.5 1.6 * * * 07/26/01 09/18/01 10/25/01 1.7 1.8 1.9 * * * * * * * * * * In Table 3 (Module 4), FG676 Fine-Pitch BGA -- XCV405E, the following pins are no longer labeled as VREF: B7, G16, G26, W26, AF20, AF8, Y1, H1. Min values added to Virtex-E Electrical Characteristics tables. Updated speed grade -8 numbers in Virtex-E Electrical Characteristics tables (Module 3). Updated minimums in Table 11 (Module 2), and added notes to Table 12 (Module 2). Added to note 2 of Absolute Maximum Ratings (Module 3). Changed all minimum hold times to -0.4 for Global Clock Set-Up and Hold for LVTTL Standard, with DLL (Module 3). Revised maximum TDLLPW in -6 speed grade for DLL Timing Parameters (Module 3). In Table 4, FG676 Fine-Pitch BGA -- XCV405E, pin B19 is no longer labeled as VREF, and pin G16 is now labeled as VREF. Updated values in Virtex-E Switching Characteristics tables. Converted data sheet to modularized format. See the Virtex-E Extended Memory Data Sheet section. Updated values in Virtex-E Switching Characteristics tables. Under Absolute Maximum Ratings, changed (TSOL) to 220 C . Changes made to SSTL symbol names in IOB Input Switching Characteristics Standard Adjustments table. Removed TSOL parameter and added footnote to Absolute Maximum Ratings table. Reworded power supplies footnote to Absolute Maximum Ratings table. Updated the speed grade designations used in data sheets, and added Table 1, which shows the current speed grade designation for each device. Updated Power-On Power Supply Requirements table. Updated the XCV405E device speed grade designation to Preliminary in Table 1. Updated Power-On Power Supply Requirements table. Updated footnotes to the DC Input and Output Levels and DLL Clock Tolerance, Jitter, and Phase Information tables. Data sheet designation upgraded from Preliminary to Production. Removed mention of MIL-M-38510/605 specification. Added link to xapp158 from the Power-On Power Supply Requirements section. Revision
09/19/00
1.2
11/20/00
1.3
11/09/01 02/01/02 07/17/02
2.0 2.1 2.2
Virtex-E Extended Memory Data Sheet
The Virtex-E Extended Memory Data Sheet contains the following modules: * * DS025-1, Virtex-E 1.8V Extended Memory FPGAs:
Introduction and Ordering Information (Module 1)
* *
DS025-3, Virtex-E 1.8V Extended Memory FPGAs:
DC and Switching Characteristics (Module 3)
DS025-2, Virtex-E 1.8V Extended Memory FPGAs:
Functional Description (Module 2)
DS025-4, Virtex-E 1.8V Extended Memory FPGAs:
Pinout Tables (Module 4)
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VirtexTM-E 1.8 V Extended Memory Field Programmable Gate Arrays
0 0
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Production Product Specification
Virtex-E Pin Definitions
Pin Name GCK0, GCK1, GCK2, GCK3 M0, M1, M2 CCLK Dedicated Pin Yes Direction Input Description Clock input pins that connect to Global Clock Buffers. These pins become user inputs when not needed for clocks. Mode pins are used to specify the configuration mode. The configuration Clock I/O pin: it is an input for SelectMAP and slave-serial modes, and output in master-serial mode. After configuration, it is input only, logic level = Don't Care. Initiates a configuration sequence when asserted Low. Indicates that configuration loading is complete, and that the start-up sequence is in progress. The output can be open drain. When Low, indicates that the configuration memory is being cleared. The pin becomes a user I/O after configuration. In SelectMAP mode, BUSY controls the rate at which configuration data is loaded. The pin becomes a user I/O after configuration unless the SelectMAP port is retained. In bit-serial modes, DOUT provides preamble and configuration data to downstream devices in a daisy-chain. The pin becomes a user I/O after configuration. D0/DIN, D1, D2, D3, D4, D5, D6, D7 WRITE No Input In SelectMAP mode, the active-low Write Enable signal. The pin becomes a user I/O after configuration unless the SelectMAP port is retained. In SelectMAP mode, the active-low Chip Select signal. The pin becomes a user I/O after configuration unless the SelectMAP port is retained. Boundary-scan Test-Access-Port pins, as defined in IEEE1149.1. No Input or Output In SelectMAP mode, D0-7 are configuration data pins. These pins become user I/Os after configuration unless the SelectMAP port is retained. In bit-serial modes, DIN is the single data input. This pin becomes a user I/O after configuration.
Yes Yes
Input Input or Output
PROGRAM DONE
Yes Yes
Input Bidirectional
INIT
No
Bidirectional (Open-drain) Output
BUSY/DOUT
No
CS
No
Input
TDI, TDO, TMS, TCK DXN, DXP VCCINT VCCO VREF GND
Yes
Mixed
Yes Yes Yes No
N/A Input Input Input
Temperature-sensing diode pins. (Anode: DXP, cathode: DXN) Power-supply pins for the internal core logic. Power-supply pins for the output drivers (subject to banking rules) Input threshold voltage pins. Become user I/Os when an external threshold voltage is not needed (subject to banking rules). Ground
Yes
Input
(c) 2000-2002 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm. All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
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BG560 Ball Grid Array Packages
XCV405E and the XCV812E Virtex-E Extended Memory devices are available in the BG560 BGA package. Pins labeled I0_VREF can be used as either in all parts unless device-dependent as indicated in the footnotes. If the pin is not used as VREF, it can be used as general I/O. Immediately following Table 1, see Table 2 for BG560 package Differential Pair information. Table 1: Bank 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BG560 BGA -- XCV405E and XCV812E Pin Description GCK3 IO IO IO IO IO IO IO_L0N IO_L0P IO_L1N_YY IO_L1P_YY IO_VREF_L2N_YY IO_L2P_YY IO_L3N_Y IO_L3P_Y IO_L4N_YY IO_L4P_YY IO_VREF_L5N_YY IO_L5P_YY IO_L6N IO_L6P IO_L7N_YY IO_L7P_YY IO_VREF_L8N_YY IO_L8P_YY IO_L9N_Y IO_L9P_Y IO_VREF_L10N_YY IO_L10P_YY IO_L11N_YY Pin# A17 A27 B25 C28 C30 D30 E18 E28 D29 D28 A31 E27 C29 B30 D27 E26 B29 D26 C27 E25 A28 D25 C26 E24 1 B26 C25 D24 E23 A25 D23
Table 1: Bank 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
BG560 BGA -- XCV405E and XCV812E Pin Description IO_L11P_YY IO_L12N IO_L12P IO_L13N_YY IO_L13P_YY IO_VREF_L14N_YY IO_L14P_YY IO_L15N_Y IO_L15P_Y IO_L16N_YY IO_L16P_YY IO_VREF_L17N_YY IO_L17P_YY IO_L18N IO_L18P IO_L19N_YY IO_L19P_YY IO_VREF_L20N_YY IO_L20P_YY IO_LVDS_DLL_L21N Pin# B24 E22 C23 A23 D22 E211 B22 D21 C21 B21 E20 D20 C20 B20 E19 D19 C19 A19 D18 C18
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
GCK2 IO IO IO IO IO_LVDS_DLL_L21P IO_L22N_Y IO_L22P_Y IO_L23N_YY IO_VREF_L23P_YY IO_L24N_YY IO_L24P_YY IO_L25N IO_L25P IO_L26N_YY IO_VREF_L26P_YY
D17 A3 D9 E8 E11 E17 C17 B17 B16 D16 E16 C16 A15 C15 D15 E15
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VirtexTM-E 1.8 V Extended Memory Field Programmable Gate Arrays Table 1: Bank 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 BG560 BGA -- XCV405E and XCV812E Pin Description IO IO IO IO IO_DOUT_BUSY_L45P_YY IO_DIN_D0_L45N_YY IO_L46P_Y IO_L46N_Y IO_L47P IO_L47N IO_VREF_L48P_Y IO_L48N_Y IO_L49P_Y IO_L49N_Y IO_L50P_Y IO_L50N_Y IO_VREF_L51P_YY IO_L51N_YY IO_L52P_Y IO_L52N_Y IO_L53P IO_L53N IO_VREF_L54P_YY IO_L54N_YY IO_L55P_Y IO_L55N_Y IO_VREF_L56P_YY IO_D1_L56N_YY IO_D2_L57P_YY IO_L57N_YY IO_L58P_Y IO_L58N_Y IO_L59P IO_L59N IO_VREF_L60P_Y IO_L60N_Y IO_L61P_Y Pin# D3 F3 G1 J2 D4 E4 F5 B3 F4 C1 G5 E3 D2 G4 H5 E2 H4 G3 J5 F1 J4 H3 K51 H2 J3 K4 L5 K3 L4 K2 M5 L3 L1 M4 N51 M2 N4
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Table 1: Bank 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
BG560 BGA -- XCV405E and XCV812E Pin Description IO_L27N_YY IO_L27P_YY IO_L28N_Y IO_L28P_Y IO_L29N_YY IO_VREF_L29P_YY IO_L30N_YY IO_L30P_YY IO_L31N IO_L31P IO_L32N_YY IO_L32P_YY IO_L33N_YY IO_VREF_L33P_YY IO_L34N IO_L34P IO_L35N_YY IO_VREF_L35P_YY IO_L36N_YY IO_L36P_YY IO_L37N_Y IO_L37P_Y IO_L38N_YY IO_VREF_L38P_YY IO_L39N_YY IO_L39P_YY IO_L40N IO_L40P IO_L41N_YY IO_VREF_L41P_YY IO_L42N_YY IO_L42P_YY IO_L43N_Y IO_L43P_Y IO_WRITE_L44N_YY IO_CS_L44P_YY Pin# C14 D14 A13 E14 C13 D131 C12 E13 A11 D12 B11 C11 B10 D11 C10 A9 C9 D101 A8 B8 E10 C8 B7 A6 C7 D8 A5 B5 C6 D7 A4 B4 C5 E7 D6 A2
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VirtexTM-E 1.8 V Extended Memory Field Programmable Gate Arrays Table 1: Bank 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 BG560 BGA -- XCV405E and XCV812E Pin Description IO_L61N_Y IO_L62P_Y IO_L62N_Y IO_VREF_L63P_YY IO_D3_L63N_YY IO_L64P_Y IO_L64N_Y IO_L65P_Y IO_L65N_Y IO_VREF_L66P_Y IO_L66N_Y IO_L67P_Y IO_L67N_Y IO_L68P_YY IO_L68N_YY Pin# N3 N2 P5 P4 P3 P2 R5 R4 R3 R1 T4 T5 T3 T2 U3 Table 1: Bank 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
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BG560 BGA -- XCV405E and XCV812E Pin Description IO_L77P IO_L77N IO_L78P IO_L78N IO_L79P_YY IO_D5_L79N_YY IO_D6_L80P_YY IO_VREF_L80N_YY IO_L81P_Y IO_L81N_Y IO_L82P_YY IO_VREF_L82N_YY IO_L83P_Y IO_L83N_Y IO_L84P_Y IO_L84N_Y IO_L85P_YY IO_VREF_L85N_YY IO_L86P_Y IO_L86N_Y IO_L87P_Y IO_L87N_Y IO_L88P_Y IO_VREF_L88N_Y IO_L89P_Y IO_L89N_Y IO_L90P_Y IO_L90N_Y IO_D7_L91P_YY IO_INIT_L91N_YY Pin# AB3 AA5 AC1 AB4 AC3 AB5 AC4 AD3 AE1 AC5 AD4 AF11 AF2 AD5 AG2 AE4 AH1 AE5 AF4 AJ1 AJ2 AF5 AG4 AK2 AJ3 AG5 AL1 AH4 AJ4 AH5
IO IO IO IO IO IO_L69P_Y IO_L69N_Y IO_L70P_Y IO_VREF_L70N_Y IO_L71P_Y IO_L71N_Y IO_L72P IO_L72N IO_D4_L73P_YY IO_VREF_L73N_YY IO_L74P_Y IO_L74N_Y IO_L75P IO_L75N IO_L76P_Y IO_VREF_L76N_Y
U4 AE3 AF3 AH3 AK3 U1 U2 V2 V4 V5 V3 W1 W3 W4 W5 Y3 Y4 AA1 Y5 AA3 AA41
3 3 3 3 3 3 3 3 3 3 3 3 3 3
4 4 4 4 4 4
GCK0 IO IO IO IO IO_L92P_YY
AL17 AJ8 AJ11 AK6 AK9 AL4
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DS025-4 (v1.6) July 17, 2002
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VirtexTM-E 1.8 V Extended Memory Field Programmable Gate Arrays Table 1: Bank 4 4 4 4 4 4 4 4 4 BG560 BGA -- XCV405E and XCV812E Pin Description IO_L111P IO_L111N IO_L112P_YY IO_L112N_YY IO_VREF_L113P_YY IO_L113N_YY IO_L114P_Y IO_L114N_Y IO_LVDS_DLL_L115P Pin# AJ15 AK15 AL15 AM16 AL16 AJ16 AK16 AN17 AM17
Table 1: Bank 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4
BG560 BGA -- XCV405E and XCV812E Pin Description IO_L92N_YY IO_L93P IO_L93N IO_L94P_YY IO_L94N_YY IO_VREF_L95P_YY IO_L95N_YY IO_L96P_Y IO_L96N_Y IO_L97P_YY IO_L97N_YY IO_VREF_L98P_YY IO_L98N_YY IO_L99P IO_L99N IO_L100P_YY IO_L100N_YY IO_VREF_L101P_YY IO_L101N_YY IO_L102P_Y IO_L102N_Y IO_VREF_L103P_YY IO_L103N_YY IO_L104P_YY IO_L104N_YY IO_L105P IO_L105N IO_L106P_YY IO_L106N_YY IO_VREF_L107P_YY IO_L107N_YY IO_L108P_Y IO_L108N_Y IO_L109P_YY IO_L109N_YY IO_VREF_L110P_YY IO_L110N_YY Pin# AJ6 AK5 AN3 AL5 AJ7 AM4 AM5 AK7 AL6 AM6 AN6 AL7 AJ9 AN7 AL8 AM8 AJ10 AL91 AM9 AK10 AN9 AL10 AM10 AL11 AJ12 AN11 AK12 AL12 AM12 AK131 AL13 AM13 AN13 AJ14 AK14 AM14 AN15
5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5
GCK1 IO IO IO IO IO IO_LVDS_DLL_L115N IO_L116P_YY IO_VREF_L116N_YY IO_L117P_YY IO_L117N_YY IO_L118P IO_L118N IO_L119P_YY IO_VREF_L119N_YY IO_L120P_YY IO_L120N_YY IO_L121P_Y IO_L121N_Y IO_L122P_YY IO_VREF_L122N_YY IO_L123P_YY IO_L123N_YY IO_L124P IO_L124N IO_L125P_YY IO_L125N_YY
AJ17 AL18 AL25 AL28 AL30 AN28 AM18 AK18 AJ18 AN19 AL19 AK19 AM20 AJ19 AL20 AN21 AL21 AJ20 AM22 AK21 AN231 AJ21 AM23 AK22 AM24 AL23 AJ22
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VirtexTM-E 1.8 V Extended Memory Field Programmable Gate Arrays Table 1: Bank 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 BG560 BGA -- XCV405E and XCV812E Pin Description IO_L126P_YY IO_VREF_L126N_YY IO_L127P_Y IO_L127N_Y IO_L128P_YY IO_VREF_L128N_YY IO_L129P_YY IO_L129N_YY IO_L130P_Y IO_L130N_Y IO_L131P_YY IO_VREF_L131N_YY IO_L132P_YY IO_L132N_YY IO_L133P_Y IO_L133N_Y IO_L134P_YY IO_VREF_L134N_YY IO_L135P_YY IO_L135N_YY IO_L136P_Y IO_L136N_Y Pin# AK23 AL24 AN26 AJ23 AK24 AM261 AM27 AJ24 AL26 AK25 AN29 AJ25 AK26 AM29 AM30 AJ26 AK27 AL29 AN31 AJ27 AM31 AK28 Table 1: Bank 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6
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BG560 BGA -- XCV405E and XCV812E Pin Description IO_L141P_Y IO_L142N_Y IO_L142P_Y IO_VREF_L143N_YY IO_L143P_YY IO_L144N_Y IO_L144P_Y IO_L145N_Y IO_L145P_Y IO_VREF_L146N_Y IO_L146P_Y IO_L147N_Y IO_L147P_Y IO_VREF_L148N_YY IO_L148P_YY IO_L149N_YY IO_L149P_YY IO_L150N_Y IO_L150P_Y IO_L151N_Y IO_L151P_Y IO_VREF_L152N_Y IO_L152P_Y IO_L153N_Y IO_L153P_Y IO_L154N_Y IO_L154P_Y IO_VREF_L155N_YY IO_L155P_YY IO_L156N_Y IO_L156P_Y IO_L157N_Y IO_L157P_Y IO_VREF_L158N_Y IO_L158P_Y IO_L159N_Y IO_L159P_Y Pin# AF29 AH32 AF30 AE29 AH33 AG33 AE30 AD29 AF32 AE311 AD30 AE32 AC29 AD31 AC30 AB29 AC31 AC33 AB30 AB31 AA29 AA301 AA31 AA32 Y29 AA33 Y30 Y32 W29 W30 W31 W33 V30 V29 V31 V32 U33
IO IO IO IO IO IO_L137N_YY IO_L137P_YY IO_L138N_Y IO_L138P_Y IO_L139N_Y IO_L139P_Y IO_VREF_L140N_Y IO_L140P_Y IO_L141N_Y
U29 AE33 AF31 AJ32 AL33 AH29 AJ30 AK31 AH30 AG29 AJ31 AK32 AG30 AH31
6 6 6 6 6 6 6 6 6 6 6 6 6 6
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DS025-4 (v1.6) July 17, 2002
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VirtexTM-E 1.8 V Extended Memory Field Programmable Gate Arrays Table 1: Bank 7 BG560 BGA -- XCV405E and XCV812E Pin Description IO_L175P_Y IO_L176N_Y IO_L176P_Y IO_L177N_YY IO_VREF_L177P_YY IO_L178N_Y IO_L178P_Y IO_L179N_Y IO_L179P_Y IO_L180N_Y IO_VREF_L180P_Y IO_L181N_Y IO_L181P_Y IO_L182N_Y IO_L182P_Y Pin# H31 J30 G32 J29 G31 E33 E32 H29 F31 D32 E31 G29 C33 F30 D31
Table 1: Bank
BG560 BGA -- XCV405E and XCV812E Pin Description Pin#
7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7
IO IO IO IO IO IO_L160N_YY IO_L160P_YY IO_L161N_Y IO_L161P_Y IO_L162N_Y IO_VREF_L162P_Y IO_L163N_Y IO_L163P_Y IO_L164N_Y IO_L164P_Y IO_L165N_YY IO_VREF_L165P_YY IO_L166N_Y IO_L166P_Y IO_L167N_Y IO_L167P_Y IO_L168N_Y IO_VREF_L168P_Y IO_L169N_Y IO_L169P_Y IO_L170N_Y IO_L170P_Y IO_L171N_YY IO_L171P_YY IO_L172N_YY IO_VREF_L172P_YY IO_L173N_Y IO_L173P_Y IO_L174N_Y IO_VREF_L174P_Y IO_L175N_Y
E30 F29 F33 G30 K30 U31 U32 T32 T30 T29 T31 R33 R31 R30 R29 P32 P31 P30 P29 M32 N31 N30 L331 M31 L32 M30 L31 M29 J33 L30 K31 L29 H33 J31 H32 1 K29
7 7 7 7 7 7 7 7 7 7 7 7 7 7
2 3 NA NA NA NA NA NA NA NA 2 NA
CCLK DONE DXN DXP M0 M1 M2 PROGRAM TCK TDI TDO TMS
C4 AJ5 AK29 AJ28 AJ29 AK30 AN32 AM1 E29 D5 E6 B33
NA NA NA NA
NC NC NC NC
C31 AC2 AK4 AL3
NA NA NA
VCCINT VCCINT VCCINT
A21 B12 B14
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VirtexTM-E 1.8 V Extended Memory Field Programmable Gate Arrays Table 1: Bank NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA BG560 BGA -- XCV405E and XCV812E Pin Description VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT Pin# B18 B28 C22 C24 E9 E12 F2 H30 J1 K32 M3 N1 N29 N33 U5 U30 Y2 Y31 AB2 AB32 AD2 AD32 AG3 AG31 AJ13 AK8 AK11 AK17 AK20 AL14 AL22 AL27 AN25 Table 1: Bank 0 0 1 1 1 1 1 2 2 2 2 2 3 3 3 3 3 4 4 4 4 4 5 5 5 5 5 6 6 6 6 6 7 7 0 0 0
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BG560 BGA -- XCV405E and XCV812E Pin Description VCCO VCCO VCCO VCCO VCCO VCCO VCCO VCCO VCCO VCCO VCCO VCCO VCCO VCCO VCCO VCCO VCCO VCCO VCCO VCCO VCCO VCCO VCCO VCCO VCCO VCCO VCCO VCCO VCCO VCCO VCCO VCCO VCCO VCCO VCCO VCCO VCCO Pin# B19 B32 A10 A16 B13 C3 E5 B2 D1 H1 M1 R2 V1 AA2 AD1 AK1 AL2 AN4 AN8 AN12 AM2 AM15 AL31 AM21 AN18 AN24 AN30 W32 AB33 AF33 AK33 AM32 C32 D33 K33 N32 T33
DS025-4 (v1.6) July 17, 2002
VCCO VCCO VCCO
A22 A26 A30
7 7 7
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VirtexTM-E 1.8 V Extended Memory Field Programmable Gate Arrays Table 1: Bank NA BG560 BGA -- XCV405E and XCV812E Pin Description GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND Pin# AD33 AE2 AG1 AG32 AH2 AJ33 AL32 AM3 AM7 AM11 AM19 AM25 AM28 AM33 AN1 AN2 AN5 AN10 AN14 AN16 AN20 AN22 AN27 AN33
Table 1: Bank
BG560 BGA -- XCV405E and XCV812E Pin Description Pin#
NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA
DS025-4 (v1.6) July 17, 2002
GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND
A1 A7 A12 A14 A18 A20 A24 A29 A32 A33 B1 B6 B9 B15 B23 B27 B31 C2 E1 F32 G2 G33 J32 K1 L2 M33 P1 P33 R32 T1 V33 W2 Y1 Y33 AB1 AC32
NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA
Notes: 1. VREF or I/O option only in the XCV812E.
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Module 4 of 4 9
VirtexTM-E 1.8 V Extended Memory Field Programmable Gate Arrays
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BG560 Differential Pin Pairs
Virtex-E Extended Memory devices have differential pin pairs that can also provide other functions when not used as a differential pair. A in the AO column indicates that the pin pair can be used as an asynchronous output for all devices provided in this package. Pairs with a note number in the AO column are device dependent. They can have asynchronous outputs if the pin pair is in the same CLB row and column in the device. Numbers in this column refer to footnotes that indicate which devices have pin pairs that can be asynchronous outputs. The Other Functions column indicates alternative function(s) not available when the pair is used as a differential pair or differential clock. Table 2: Pair BG560 Package Differential Pin Pair Summary XCV405E and XCV812E Bank P Pin N Pin AO Other Functions
Table 2: 16 17 18 19 20 21 22 23 24 25 26 27 28 IO LVDS 21 IO LVDS 21 IO LVDS 115 IO LVDS 115 29 30 31 32 33 34 35 36 VREF_0 37 38 VREF_0 VREF_0 43 1 1 2 2 2 2 2 39 40 41 42 1 1 1 1 1 1 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
BG560 Package Differential Pin Pair Summary XCV405E and XCV812E E20 C20 E19 C19 D18 E17 B17 D16 C16 C15 E15 D14 E14 D13 E13 D12 C11 D11 A9 D10 B8 C8 A6 D8 B5 D7 B4 E7 A2 D4 F5 F4 G5 D2 B21 D20 B20 D19 A19 C18 C17 B16 E16 A15 D15 C14 A13 C13 C12 A11 B11 B10 C10 C9 A8 E10 B7 C7 A5 C6 A4 C5 D6 E4 B3 C1 E3 G4 NA 1 1 NA 1 1 1 NA 1 NA 2 1 1 NA 2 NA 2 NA 1 1 VREF_0 VREF_0 GCLK LVDS 3/2 VREF_1 VREF_1 VREF_1 VREF_1 VREF_1 VREF_1 VREF_1 CS DIN_D0 VREF_2 -
Global Differential Clock 3 2 1 0 0 1 5 4 A17 D17 AJ17 AL17 C18 E17 AM18 AM17 NA NA NA NA
IO LVDS Total Outputs: 183, Asyncronous Outputs: 79 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 D29 A31 C29 D27 B29 C27 A28 C26 B26 D24 A25 B24 C23 D22 B22 C21 E28 D28 E27 B30 E26 D26 E25 D25 E24 C25 E23 D23 E22 A23 E21 D21 NA 1 NA 1 1 1 NA 1 -
44 VREF_0 VREF_0 49 45 46 47 48
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DS025-4 (v1.6) July 17, 2002
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VirtexTM-E 1.8 V Extended Memory Field Programmable Gate Arrays Table 2: 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 3 3 3 3 3 3 3 3 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 5 5 5 BG560 Package Differential Pin Pair Summary XCV405E and XCV812E AG2 AH1 AF4 AJ2 AG4 AJ3 AL1 AJ4 AL4 AK5 AL5 AM4 AK7 AM6 AL7 AN7 AM8 AL9 AK10 AL10 AL11 AN11 AL12 AK13 AM13 AJ14 AM14 AJ15 AL15 AL16 AK16 AM17 AK18 AN19 AE4 AE5 AJ1 AF5 AK2 AG5 AH4 AH5 AJ6 AN3 AJ7 AM5 AL6 AN6 AJ9 AL8 AJ10 AM9 AN9 AM10 AJ12 AK12 AM12 AL13 AN13 AK14 AN15 AK15 AM16 AJ16 AN17 AM18 AJ18 AL19 NA NA 2 1 NA NA NA 1 NA 1 1 1 NA 1 NA 1 1 1 NA 1 1 VREF_3 VREF_3 INIT VREF_4 VREF_4 VREF_4 VREF_4 VREF_4 VREF_4 VREF_4 GCLK LVDS 1/0 VREF_5 -
Table 2: 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
BG560 Package Differential Pin Pair Summary XCV405E and XCV812E H5 H4 J5 J4 K5 J3 L5 L4 M5 L1 N5 N4 N2 P4 P2 R4 R1 T5 T2 U1 V2 V5 W1 W4 Y3 AA1 AA3 AB3 AC1 AC3 AC4 AE1 AD4 AF2 E2 G3 F1 H3 H2 K4 K3 K2 L3 M4 M2 N3 P5 P3 R5 R3 T4 T3 U3 U2 V4 V3 W3 W5 Y4 Y5 AA4 AA5 AB4 AB5 AD3 AC5 AF1 AD5 NA NA 2 NA NA 2 NA 1 1 NA 2 NA NA NA NA NA NA 2 NA 1 1 NA 2 1 NA NA VREF_2 VREF_2 D1 D2 VREF_2 D3 VREF_2 IRDY VREF_3 VREF_3 VREF_3 D5 VREF_3 VREF_3 -
DS025-4 (v1.6) July 17, 2002
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Module 4 of 4 11
VirtexTM-E 1.8 V Extended Memory Field Programmable Gate Arrays Table 2: 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 BG560 Package Differential Pin Pair Summary XCV405E and XCV812E AK19 AJ19 AN21 AJ20 AK21 AJ21 AK22 AL23 AK23 AN26 AK24 AM27 AL26 AN29 AK26 AM30 AK27 AN31 AM31 AJ30 AH30 AJ31 AG30 AF29 AF30 AH33 AE30 AF32 AD30 AC29 AC30 AC31 AB30 AA29 AM20 AL20 AL21 AM22 AN23 AM23 AM24 AJ22 AL24 AJ23 AM26 AJ24 AK25 AJ25 AM29 AJ26 AL29 AJ27 AK28 AH29 AK31 AG29 AK32 AH31 AH32 AE29 AG33 AD29 AE31 AE32 AD31 AB29 AC33 AB31 NA 1 NA 2 1 1 NA 2 NA 2 NA 1 1 NA 2 NA NA NA 2 NA VREF_5 VREF_5 VREF_5 VREF_5 VREF_5 VREF_5 VREF_6 VREF_6 VREF_6 VREF_6 Table 2: 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 6 6 6 6 6 6 6 6 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7
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BG560 Package Differential Pin Pair Summary XCV405E and XCV812E AA31 Y29 Y30 W29 W31 V30 V31 U33 U32 T30 T31 R31 R29 P31 P29 N31 L33 L32 L31 J33 K31 H33 H32 H31 G32 G31 E32 F31 E31 C33 D31 AA30 AA32 AA33 Y32 W30 W33 V29 V32 U31 T32 T29 R33 R30 P32 P30 M32 N30 M31 M30 M29 L30 L29 J31 K29 J30 J29 E33 H29 D32 G29 F30 1 1 NA 2 NA NA NA NA NA NA 2 NA 1 1 NA 2 1 NA NA NA NA 2 1 NA NA VREF_6 VREF_6 VREF_6 IRDY VREF_7 VREF_7 VREF_7 VREF_7 VREF_7 VREF_7 VREF_7 -
Notes: 1. AO in the XCV812E 2. AO in the XCV405E
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DS025-4 (v1.6) July 17, 2002
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VirtexTM-E 1.8 V Extended Memory Field Programmable Gate Arrays Table 3: Bank 0 0 0 0 FG676 Fine-Pitch BGA -- XCV405E Pin Description IO_L11N_YY IO_L11P_YY IO_L12N_Y IO_L12P_Y IO_L13N_YY IO_L13P_YY IO_L14N_YY IO_L14P_YY IO_L15N IO_L15P IO_L16N_YY IO_L16P_YY IO_VREF_L17N_YY IO_L17P_YY IO_L18N_YY IO_L18P_YY IO_L19N_Y IO_L19P_Y IO_VREF_L20N_Y IO_L20P_Y IO_LVDS_DLL_L21N Pin # C9 F10 A8 E10 G11 D10 B10 F11 C10 E11 G12 D11 C11 F12 A11 E12 D12 C12 A12 H13 B13
FG676 Fine-Pitch Ball Grid Array Package
XCV405E Virtex-E Extended Memory devices are available in the FG676 fine-pitch BGA package. Pins labeled I0_VREF can be used as either. If the pin is not used as VREF, it can be used as general I/O. Immediately following Table 3, see Table 4 for FG676 package Differential Pair information. Table 3: Bank 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FG676 Fine-Pitch BGA -- XCV405E Pin Description GCK3 IO IO IO IO IO IO IO_L0N_Y IO_L0P_Y IO_L1N_YY IO_L1P_YY IO_VREF_L2N_YY IO_L2P_YY IO_L3N IO_L3P IO_L4N IO_L4P IO_VREF_L5N_YY IO_L5P_YY IO_L6N_YY IO_L6P_YY IO_L7N_Y IO_L7P_Y IO_L8N_Y IO_L8P_Y IO_L9N IO_L9P IO_L10N IO_VREF_L10P Pin # E13 A6 B3 C6 C8 D5 G13 C4 F7 G8 C5 D6 E7 A4 F8 B5 D7 E8 G9 A5 F9 D8 C7 B7 E9 A7 D9 B8 G10
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
1 1 1 1 1 1 1 1 1 1 1 1 1
GCK2 IO IO IO IO IO_LVDS_DLL_L21P IO_L22N IO_L22P IO_L23N_Y IO_VREF_L23P_Y IO_L24N_Y IO_L24P_Y IO_L25N_YY
C13 A19 A20 A22 B23 F14 E14 F13 D14 A14 C14 H14 G14
DS025-4 (v1.6) July 17, 2002
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Module 4 of 4 13
VirtexTM-E 1.8 V Extended Memory Field Programmable Gate Arrays Table 3: Bank 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FG676 Fine-Pitch BGA -- XCV405E Pin Description IO_L25P_YY IO_L26N_YY IO_VREF_L26P_YY IO_L27N_YY IO_L27P_YY IO_L28N IO_L28P IO_L29N_YY IO_L29P_YY IO_L30N_YY IO_L30P_YY IO_L31N_Y IO_L31P_Y IO_L32N_YY IO_L32P_YY IO_L33N_YY IO_VREF_L33P_YY IO_L34N_YY IO_L34P_YY IO_L35N_Y IO_L35P_Y IO_L36N_Y IO_L36P_Y IO_L37N_YY IO_L37P_YY IO_L38N_YY IO_VREF_L38P_YY IO_L39N_YY IO_L39P_YY IO_L40N_YY IO_L40P_YY IO_L41N_YY IO_VREF_L41P_YY IO_L42N_YY IO_L42P_YY Pin # C15 E15 D15 C16 F15 G15 D16 E16 A17 C17 E17 F16 D17 F17 C18 A18 G16 C19 G17 D18 B19 D19 E18 F18 B20 G19 C20 G18 E19 A21 D20 F19 C21 B22 E20 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 IO IO IO IO_D1 IO_DOUT_BUSY_L45P_YY IO_DIN_D0_L45N_YY IO_L46P_YY IO_L46N_YY IO_L47P_Y IO_L47N_Y IO_VREF_L48P_Y IO_L48N_Y IO_L49P_Y IO_L49N_Y IO_L50P_YY IO_L50N_YY IO_VREF_L51P_YY IO_L51N_YY IO_L52P_YY IO_L52N_YY IO_L53P_Y IO_L53N_Y IO_L54P_Y IO_L54N_Y IO_L55P_YY IO_L55N_YY IO_L56P_YY IO_VREF_L56N_YY IO_D2_L57P_YY IO_L57N_YY D26 E26 F26 K24 E23 F22 E24 F20 G21 G22 F24 H20 E25 H21 F23 G23 H23 J20 G24 H22 J21 G25 G26 J22 H24 J23 J24 K20 K22 K21 Table 3: Bank 1 1 1 1 FG676 Fine-Pitch BGA -- XCV405E Pin Description IO_L43N_Y IO_L43P_Y IO_WRITE_L44N_YY IO_CS_L44P_YY Pin # A23 D21 C22 E21
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VirtexTM-E 1.8 V Extended Memory Field Programmable Gate Arrays Table 3: Pin # H25 K23 L20 J26 K25 L22 L21 L23 M20 L24 M23 M22 L26 M21 N19 M24 M26 N20 N24 N21 N23 N22 Bank 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 FG676 Fine-Pitch BGA -- XCV405E Pin Description IO_L72N_YY IO_D4_L73P_YY IO_VREF_L73N_YY IO_L74P_Y IO_L74N_Y IO_L75P_Y IO_L75N_Y IO_L76P_Y IO_L76N_Y IO_L77P_Y IO_L77N_Y IO_L78P_YY IO_L78N_YY IO_L79P_YY IO_D5_L79N_YY IO_D6_L80P_YY IO_VREF_L80N_YY IO_L81P_YY IO_L81N_YY IO_L82P_Y IO_L82N_Y IO_L83P_Y IO_L83N_Y IO_L84P_YY IO_L84N_YY IO_L85P_YY IO_VREF_L85N_YY IO_L86P_Y IO_L86N_Y IO_L87P_Y IO_L87N_Y IO_L88P_Y IO_VREF_L88N_Y IO_L89P_Y IO_L89N_Y Pin # R22 R24 R23 T24 R20 T22 U24 T23 U25 T21 U20 U22 V26 T20 U23 V24 U21 V23 W24 V22 W26 Y25 V21 V20 AA26 Y24 W23 AA24 Y23 AB26 W21 Y22 W22 AA23 AB24
Table 3: Bank 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
FG676 Fine-Pitch BGA -- XCV405E Pin Description IO_L58P_YY IO_L58N_YY IO_L59P_Y IO_L59N_Y IO_L60P_Y IO_L60N_Y IO_L61P_Y IO_L61N_Y IO_L62P_Y IO_L62N_Y IO_VREF_L63P_YY IO_D3_L63N_YY IO_L64P_YY IO_L64N_YY IO_L65P_Y IO_L65N_Y IO_VREF_L66P_Y IO_L66N_Y IO_L67P_YY IO_L67N_YY IO_L68P_YY IO_L68N_YY
3 3 3 3 3 3 3 3 3 3 3 3
IO IO IO IO IO IO_L69P_YY IO_L69N_YY IO_L70P_Y IO_VREF_L70N_Y IO_L71P_Y IO_L71N_Y IO_L72P_YY
P24 W25 Y26 AB25 AC26 P21 P23 P22 R25 P19 P20 R21
3 3 3 3 3 3 3 3 3 3 3 3
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VirtexTM-E 1.8 V Extended Memory Field Programmable Gate Arrays Table 3: Bank 3 3 3 3 FG676 Fine-Pitch BGA -- XCV405E Pin Description IO_L90P_YY IO_L90N_YY IO_D7_L91P_YY IO_INIT_L91N_YY Pin # W20 AC24 AB23 Y21 Table 3: Bank 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 GCK0 IO IO IO IO IO_L92P_YY IO_L92N_YY IO_L93P_Y IO_L93N_Y IO_L94P_YY IO_L94N_YY IO_VREF_L95P_YY IO_L95N_YY IO_L96P IO_L96N IO_L97P IO_L97N IO_VREF_L98P_YY IO_L98N_YY IO_L99P_YY IO_L99N_YY IO_L100P_Y IO_L100N_Y IO_L101P_Y IO_L101N_Y IO_L102P IO_L102N IO_L103P IO_VREF_L103N IO_L104P_YY AA14 AC18 AE20 AE23 AF21 AC22 AD26 AD23 AA20 Y19 AC21 AD22 AB20 AE22 Y18 AF22 AA19 AD21 AB19 AC20 AA18 AC19 AD20 AF20 AB18 AD19 Y17 AE19 AD18 AF19 5 5 5 5 5 5 5 5 5 5 5 5 GCK1 IO IO IO IO IO IO_LVDS_DLL_L115N IO_L116P_Y IO_VREF_L116N_Y IO_L117P_Y IO_L117N_Y IO_L118P_YY AB13 AD7 AD13 AE4 AE7 AF5 AF13 AA13 AF12 AC13 W13 AA12 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 FG676 Fine-Pitch BGA -- XCV405E Pin Description IO_L104N_YY IO_L105P_Y IO_L105N_Y IO_L106P_YY IO_L106N_YY IO_L107P_YY IO_L107N_YY IO_L108P IO_L108N IO_L109P_YY IO_L109N_YY IO_VREF_L110P_YY IO_L110N_YY IO_L111P_YY IO_L111N_YY IO_L112P_Y IO_L112N_Y IO_VREF_L113P_Y IO_L113N_Y IO_L114P IO_L114N IO_LVDS_DLL_L115P Pin # AA17 AC17 AB17 Y16 AE17 AF17 AA16 AD17 AB16 AC16 AD16 AC15 Y15 AD15 AA15 W14 AB15 AF15 Y14 AD14 AB14 AC14
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VirtexTM-E 1.8 V Extended Memory Field Programmable Gate Arrays Table 3: Pin # AD12 AC12 AB12 AD11 Y12 AB11 AD10 AC11 AE10 AC10 AA11 Y11 AD9 AB10 AF9 AD8 AA10 AE8 Y10 AC9 AF8 AF7 AB9 AA9 AF6 AC8 AC7 AD6 Y9 AE5 AA8 AC6 AB8 AD5 AA7 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 IO IO IO IO IO IO_L137N_YY IO_L137P_YY IO_L138N_YY IO_L138P_YY IO_L139N_Y IO_L139P_Y IO_VREF_L140N_Y IO_L140P_Y IO_L141N_Y IO_L141P_Y IO_L142N_YY IO_L142P_YY IO_VREF_L143N_YY IO_L143P_YY IO_L144N_YY IO_L144P_YY IO_L145N_Y IO_L145P_Y IO_L146N_Y IO_L146P_Y IO_L147N_YY IO_L147P_YY IO_L148N_YY IO_VREF_L148P_YY IO_L149N_YY IO_L149P_YY IO_L150N_YY P3 AA3 W3 Y2 Y6 AA5 AC3 AC2 AB4 W6 AA4 AB3 Y5 AB2 V7 AB1 Y4 V5 W5 AA1 V6 W4 Y3 Y1 U7 W1 V4 W2 U6 V3 T5 U5 Bank 5 5 FG676 Fine-Pitch BGA -- XCV405E Pin Description IO_L136P_Y IO_L136N_Y Pin # AF4 AC5
Table 3: Bank 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5
FG676 Fine-Pitch BGA -- XCV405E Pin Description IO_L118N_YY IO_L119P_YY IO_VREF_L119N_YY IO_L120P_YY IO_L120N_YY IO_L121P IO_L121N IO_L122P_YY IO_L122N_YY IO_L123P_YY IO_L123N_YY IO_L124P_Y IO_L124N_Y IO_L125P_YY IO_L125N_YY IO_L126P_YY IO_VREF_L126N_YY IO_L127P_YY IO_L127N_YY IO_L128P_Y IO_L128N_Y IO_L129P_Y IO_L129N_Y IO_L130P_YY IO_L130N_YY IO_L131P_YY IO_VREF_L131N_YY IO_L132P_YY IO_L132N_YY IO_L133P_YY IO_L133N_YY IO_L134P_YY IO_VREF_L134N_YY IO_L135P_YY IO_L135N_YY
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VirtexTM-E 1.8 V Extended Memory Field Programmable Gate Arrays Table 3: Bank 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 FG676 Fine-Pitch BGA -- XCV405E Pin Description IO_L150P_YY IO_L151N_Y IO_L151P_Y IO_L152N_Y IO_L152P_Y IO_L153N_Y IO_L153P_Y IO_L154N_Y IO_L154P_Y IO_VREF_L155N_YY IO_L155P_YY IO_L156N_YY IO_L156P_YY IO_L157N_Y IO_L157P_Y IO_VREF_L158N_Y IO_L158P_Y IO_L159N_YY IO_L159P_YY Pin # U4 T7 U3 U2 T6 U1 T4 R7 T3 R4 R6 R3 R5 P8 P7 R1 P6 P5 P4 Table 3: Bank 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 IO IO IO IO IO IO_L160N_YY IO_L160P_YY IO_L161N_YY IO_L161P_YY IO_L162N_Y IO_VREF_L162P_Y IO_L163N_Y IO_L163P_Y IO_L164N_YY IO_L164P_YY D2 D3 E1 G1 H2 N5 N8 N6 N3 N4 M2 N7 M7 M6 M3 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 FG676 Fine-Pitch BGA -- XCV405E Pin Description IO_L165N_YY IO_VREF_L165P_YY IO_L166N_Y IO_L166P_Y IO_L167N_Y IO_L167P_Y IO_L168N_Y IO_L168P_Y IO_L169N_Y IO_L169P_Y IO_L170N_YY IO_L170P_YY IO_L171N_YY IO_L171P_YY IO_L172N_YY IO_VREF_L172P_YY IO_L173N_YY IO_L173P_YY IO_L174N_Y IO_L174P_Y IO_L175N_Y IO_L175P_Y IO_L176N_YY IO_L176P_YY IO_L177N_YY IO_VREF_L177P_YY IO_L178N_Y IO_L178P_Y IO_L179N_Y IO_L179P_Y IO_L180N_Y IO_VREF_L180P_Y IO_L181N_Y IO_L181P_Y IO_L182N_YY Pin # M4 M5 L3 L7 L6 K2 L4 K1 K3 L5 K5 J3 K4 J4 H3 K6 K7 G3 J5 H1 G2 J6 J7 F1 H4 G4 F3 H5 E2 H6 G5 F4 H7 G6 E3
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VirtexTM-E 1.8 V Extended Memory Field Programmable Gate Arrays Table 3: Pin # E4 Bank 4 4 FG676 Fine-Pitch BGA -- XCV405E Pin Description NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC Pin # AE15 AF14 AF16 AF18 AF23 AE12 AF3 AF10 AF11 Y13 AC1 P1 R2 T1 V1 D1 J1 L1 M1 N1 T25 T2 P2 N25 L25 L2 F6 F25 F21 F2 C26 C25 C2 C1 B6
Table 3: Bank 7
FG676 Fine-Pitch BGA -- XCV405E Pin Description IO_L182P_YY
2 3 NA NA NA NA NA NA NA NA 2 NA
CCLK DONE DXN DXP M0 M1 M2 PROGRAM TCK TDI TDO TMS
D24 AB21 AB7 Y8 AD4 W7 AB6 AA22 E6 D22 C23 F5
4 4 4 5 5 5 5 5 6 6 6 6 6
0 0 0 0 0 1 1 1 1 1 2 2 2 2 2 3 3 3 3 3
NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC
A9 A10 B4 B12 D13 A13 A16 A24 B15 B17 D25 H26 K26 M25 N26 AC25 P26 R26 T26 U26
7 7 7 7 7 NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA
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VirtexTM-E 1.8 V Extended Memory Field Programmable Gate Arrays Table 3: Bank NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA FG676 Fine-Pitch BGA -- XCV405E Pin Description NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC Pin # B26 B24 B21 B16 B11 B1 AF25 AF24 AF2 AE6 AE3 AE26 AE24 AE21 AE16 AE14 AE11 AE1 AD25 AD2 AD1 AA6 AA25 AA21 AA2 A3 A25 A2 A15 0 0 0 0 0 0 NA NA NA NA NA VCCINT VCCINT VCCINT VCCINT VCCINT G7 G20 H8 H19 J9 1 1 1 1 1 VCCO VCCO VCCO VCCO VCCO VCCO VCCO VCCO VCCO VCCO VCCO J13 J12 H9 H12 H11 H10 J15 J14 H18 H17 H16 Table 3: Bank NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA FG676 Fine-Pitch BGA -- XCV405E Pin Description VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT Pin # J10 J11 J16 J17 J18 K9 K18 L9 L18 T9 T18 U9 U18 V9 V10 V11 V16 V17 V18 Y7 Y20 W8 W19
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VirtexTM-E 1.8 V Extended Memory Field Programmable Gate Arrays Table 3: Pin # H15 N18 M19 M18 L19 K19 J19 V19 U19 T19 R19 R18 P18 W18 W17 W16 W15 V15 V14 W9 W12 W11 W10 V13 V12 V8 U8 T8 R9 R8 P9 N9 M9 M8 L8 NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND V25 V2 U17 U16 U15 U14 U13 U12 U11 U10 T17 T16 T15 T14 T13 T12 T11 T10 R17 R16 R15 R14 R13 R12 R11 R10 P25 P17 P16 P15 P14 P13 Bank 7 7 FG676 Fine-Pitch BGA -- XCV405E Pin Description VCCO VCCO Pin # K8 J8
Table 3: Bank 1 2 2 2 2 2 2 3 3 3 3 3 3 4 4 4 4 4 4 5 5 5 5 5 5 6 6 6 6 6 6 7 7 7 7
FG676 Fine-Pitch BGA -- XCV405E Pin Description VCCO VCCO VCCO VCCO VCCO VCCO VCCO VCCO VCCO VCCO VCCO VCCO VCCO VCCO VCCO VCCO VCCO VCCO VCCO VCCO VCCO VCCO VCCO VCCO VCCO VCCO VCCO VCCO VCCO VCCO VCCO VCCO VCCO VCCO VCCO
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VirtexTM-E 1.8 V Extended Memory Field Programmable Gate Arrays Table 3: Bank NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA FG676 Fine-Pitch BGA -- XCV405E Pin Description GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND Pin # P12 P11 P10 N2 N17 N16 N15 N14 N13 N12 N11 N10 M17 M16 M15 M14 M13 M12 M11 M10 L17 L16 L15 L14 L13 L12 L11 L10 K17 K16 K15 K14 K13 K12 K11 Table 3: Bank NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA FG676 Fine-Pitch BGA -- XCV405E Pin Description GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND Pin # K10 J25 J2 E5 E22 D4 D23 C3 C24 B9 B25 B2 B18 B14 AF26 AF1 AE9 AE25 AE2 AE18 AE13 AD3 AD24 AC4 AC23 AB5 AB22 A26 A1
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VirtexTM-E 1.8 V Extended Memory Field Programmable Gate Arrays Table 4: FG676 Fine-Pitch BGA Differential Pin Pair Summary -- XCV405E P Pair 16 17 18 19 20 21 22 23 24 25 26 IO_DLL_L21N IO_DLL_L21P IO_DLL_L115 N IO_DLL_L115P 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 Bank 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 Pin D11 F12 E12 C12 H13 F14 F13 A14 H14 C15 D15 F15 D16 A17 E17 D17 C18 G16 G17 B19 E18 B20 C20 E19 D20 C21 E20 D21 E21 E23 E24 G21 F24 E25 N Pin G12 C11 A11 D12 A12 B13 E14 D14 C14 G14 E15 C16 G15 E16 C17 F16 F17 A18 C19 D18 D19 F18 G19 G18 A21 F19 B22 A23 C22 F22 F20 G22 H20 H21 AO NA NA NA NA NA NA NA NA NA 2 2 1 1 Other Functions VREF VREF IO_LVDS_DLL VREF VREF VREF VREF VREF CS DIN, D0 VREF -
FG676 Differential Pin Pairs
Virtex-E Extended Memory devices have differential pin pairs that can also provide other functions when not used as a differential pair. A in the AO column indicates that the pin pair can be used as an asynchronous output for all devices provided in this package. Pairs with a note number in the AO column are device dependent. They can have asynchronous outputs if the pin pair is in the same CLB row and column in the device. Numbers in this column refer to footnotes that indicate which devices have pin pairs that can be asynchronous outputs. The Other Functions column indicates alternative function(s) not available when the pair is used as a differential pair or differential clock. Table 4: FG676 Fine-Pitch BGA Differential Pin Pair Summary -- XCV405E P Pair Bank Pin N Pin AO Other Functions
Global Differential Clock 3 2 1 0 0 1 5 4 E13 C13 AB13 AA14 B13 F14 AF13 AC14 NA NA NA NA
IOLVDS Total Pairs: 183, Asynchronous Output Pairs: 97 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 F7 C5 E7 F8 D7 G9 F9 C7 E9 D9 G10 F10 E10 D10 F11 E11 C4 G8 D6 A4 B5 E8 A5 D8 B7 A7 B8 C9 A8 G11 B10 C10 NA NA NA NA NA NA NA NA NA VREF VREF VREF -
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VirtexTM-E 1.8 V Extended Memory Field Programmable Gate Arrays Table 4: FG676 Fine-Pitch BGA Differential Pin Pair Summary -- XCV405E P Pair 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 Bank 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 Pin F23 H23 G24 J21 G26 H24 J24 K22 H25 L20 K25 L21 M20 M23 L26 N19 M26 N24 N23 P21 P22 P19 R21 R24 T24 T22 T23 T21 U22 T20 V24 V23 V22 Y25 N Pin G23 J20 H22 G25 J22 J23 K20 K21 K23 J26 L22 L23 L24 M22 M21 M24 N20 N21 N22 P23 R25 P20 R22 R23 R20 U24 U25 U20 V26 U23 U21 W24 W26 V21 AO 2 1 2 1 1 1 2 1 1 2 1 1 1 2 NA NA Other Functions VREF VREF D2 D3 VREF VREF VREF D5 VREF Pair 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 Bank 3 3 3 3 3 3 3 3 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 5 5 5 Table 4: FG676 Fine-Pitch BGA Differential Pin Pair Summary -- XCV405E P Pin V20 Y24 AA24 AB26 Y22 AA23 W20 AB23 AC22 AD23 Y19 AD22 AE22 AF22 AD21 AC20 AC19 AF20 AD19 AE19 AF19 AC17 Y16 AF17 AD17 AC16 AC15 AD15 W14 AF15 AD14 AC14 AA13 AC13 N Pin AA26 W23 Y23 W21 W22 AB24 AC24 Y21 AD26 AA20 AC21 AB20 Y18 AA19 AB19 AA18 AD20 AB18 Y17 AD18 AA17 AB17 AE17 AA16 AB16 AD16 Y15 AA15 AB15 Y14 AB14 AF13 AF12 W13 AO NA NA NA NA NA1 NA NA NA NA NA NA NA NA NA NA NA NA NA NA Other Functions VREF VREF INIT VREF VREF VREF VREF VREF IO_LVDS_DLL VREF -
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VirtexTM-E 1.8 V Extended Memory Field Programmable Gate Arrays Table 4: FG676 Fine-Pitch BGA Differential Pin Pair Summary -- XCV405E P Pair 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 Bank 6 6 6 6 6 6 6 6 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 Pin T6 T4 T3 R6 R5 P7 P6 P4 N8 N3 M2 M7 M3 M5 L7 K2 K1 L5 J3 J4 K6 G3 H1 J6 F1 G4 H5 H6 F4 G6 E4 N Pin U2 U1 R7 R4 R3 P8 R1 P5 N5 N6 N4 N7 M6 M4 L3 L6 L4 K3 K5 K4 H3 K7 J5 G2 J7 H4 F3 E2 G5 H7 E3 AO NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA Other Functions VREF VREF VREF VREF VREF VREF VREF -
Table 4:
FG676 Fine-Pitch BGA Differential Pin Pair Summary -- XCV405E P N Pin AD12 AB12 Y12 AD10 AE10 AA11 AD9 AF9 AA10 Y10 AF8 AB9 AF6 AC7 Y9 AA8 AB8 AA7 AC5 AA5 AC2 W6 AB3 AB2 AB1 V5 AA1 W4 Y1 W1 W2 V3 U5 T7 AO NA NA NA NA NA NA NA NA NA NA NA Other Functions VREF VREF VREF VREF VREF VREF VREF -
Pair 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151
Bank 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6
Pin AA12 AC12 AD11 AB11 AC11 AC10 Y11 AB10 AD8 AE8 AC9 AF7 AA9 AC8 AD6 AE5 AC6 AD5 AF4 AC3 AB4 AA4 Y5 V7 Y4 W5 V6 Y3 U7 V4 U6 T5 U4 U3
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VirtexTM-E 1.8 V Extended Memory Field Programmable Gate Arrays
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FG900 Fine-Pitch Ball Grid Array Package
The XCV812E Virtex-E Extended Memory devices are available in the FG900 fine-pitch BGA package. Pins labeled I0_VREF can be used as either. If the pin is not used as VREF, it can be used as general I/O. Immediately following Table 5, see Table 6 for FG900 package Differential Pair information. Table 5: Bank 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FG900 Fine-Pitch BGA Package -- XCV812E Description GCK3 IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO_VREF IO_L1N_Y IO_L1P_Y IO_L2N_Y IO_L2P_Y IO_L4N_YY IO_L4P_YY IO_VREF_L5N_YY IO_L5P_YY IO_L6N IO_L6P IO_L7N IO_L7P Pin C15 A7 A13 C9 C10 D10 E6 F7 F9 F15 G12 G15 H15 J10 K12 A9 D5 G8 A3 H9 A4 D6 E7 B5 A5 F8 D7 N11
Table 5: Bank 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
FG900 Fine-Pitch BGA Package -- XCV812E Description IO_L8N_YY IO_L8P_YY IO_VREF_L9N_YY IO_L9P_YY IO_L10N IO_L10P IO_L11N IO_L11P IO_L12N_YY IO_L12P_YY IO_VREF_L13N_YY IO_L13P_YY IO_L15N IO_L15P IO_L17N IO_L17P IO_L19N_Y IO_L19P_Y IO_L20N_Y IO_L20P_Y IO_L22N_YY IO_L22P_YY IO_VREF_L23N_YY IO_L23P_YY IO_L24N IO_L24P IO_L25N IO_L25P IO_L26N_YY IO_L26P_YY IO_VREF_L27N_YY IO_L27P_YY IO_L28N IO_L28P Pin G9 E8 A6 J11 C7 B7 C8 H10 G10 F10 A8 H11 B9 J12 G11 B10 H13 F11 E11 D11 F12 C11 A10 D12 E12 A11 G13 B12 A12 K13 F13 B13 G14 E13
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VirtexTM-E 1.8 V Extended Memory Field Programmable Gate Arrays Table 5: Bank 1 1 1 1 1 1 1 1 FG900 Fine-Pitch BGA Package -- XCV812E Description IO_L43P IO_L44N IO_L44P IO_L45N_YY IO_VREF_L45P_YY IO_L46N_YY IO_L46P_YY IO_L48N_Y IO_L48P_Y IO_L49N_Y IO_L49P_Y IO_L51N_YY IO_L51P_YY IO_L52N_YY IO_VREF_L52P_YY IO_L53N IO_L53P IO_L54N IO_L54P IO_L55N_YY IO_VREF_L55P_YY IO_L56N_YY IO_L56P_YY IO_L57N IO_L57P IO_L58N IO_L58P IO_L59N_YY IO_VREF_L59P_YY IO_L60N_YY IO_L60P_YY IO_L61N IO_L61P IO_L62N Pin G18 D19 H18 F18 F19 B20 K17 G19 C20 K18 E20 F20 A21 C21 A22 H19 B22 E21 D22 F21 C22 H20 E22 G21 A23 A24 K19 C24 B24 H21 G22 E23 C25 D24
Table 5: Bank 0 0 0 0 0 0 0
FG900 Fine-Pitch BGA Package -- XCV812E Description IO_L29N IO_L29P IO_L30N_YY IO_L30P_YY IO_VREF_L31N_YY IO_L31P_YY IO_LVDS_DLL_L34N Pin D14 B14 A14 J14 K14 J15 A15
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
GCk2 IO IO IO IO IO IO IO IO_LVDS_DLL_L34P IO_L35N IO_L35P IO_L36N IO_L36P IO_L37N_YY IO_VREF_L37P_YY IO_L38N_YY IO_L38P_YY IO_L39N IO_L39P IO_L40N IO_L40P IO_L41N_YY IO_VREF_L41P_YY IO_L42N_YY IO_L42P_YY IO_L43N
E15 B18 B21 B28 C23 C26 D20 D23 E16 B16 F16 A16 H16 C16 K15 K16 G16 A17 E17 F17 C17 E18 A18 D18 A19 B19
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
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VirtexTM-E 1.8 V Extended Memory Field Programmable Gate Arrays Table 5: Bank 1 1 1 1 1 1 1 1 1 1 1 FG900 Fine-Pitch BGA Package -- XCV812E Description IO_L62P IO_L63N_YY IO_VREF_L63P_YY IO_L64N_YY IO_L64P_YY IO_L66N_Y IO_L66P_Y IO_L67N_Y IO_L67P_Y IO_WRITE_L69N_YY IO_CS_L69P_YY Pin A26 B26 K20 D25 J21 B27 G23 A27 F24 K21 C27 Table 5: Bank 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 IO IO IO IO IO IO IO IO IO IO IO IO IO IO_DOUT_BUSY_L70P_YY IO_DIN_D0_L70N_YY IO_L72P_Y IO_L72N_Y IO_L73P IO_L73N IO_L75P IO_L75N IO_VREF_L76P_Y D28 F27 H25 J25 J28 K28 K30 M23 N20 N23 R27 R28 R30 J22 E27 G25 E25 E28 C30 D30 J23 L21 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
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FG900 Fine-Pitch BGA Package -- XCV812E Description IO_L76N_Y IO_L77P_YY IO_L77N_YY IO_L78P IO_L78N IO_L79P IO_L79N IO_VREF_L80P_YY IO_L80N_YY IO_L81P_YY IO_L81N_YY IO_L82P_Y IO_L82N_Y IO_L83P IO_L83N IO_VREF_L84P IO_L84N IO_L86P IO_L86N IO_VREF IO_D1_L88P IO_D2_L88N IO_L90P_Y IO_L90N_Y IO_L91P IO_L91N IO_L93P IO_L93N IO_VREF_L94P_Y IO_L94N_Y IO_L95P_YY IO_L95N_YY IO_L96P IO_L96N Pin F28 G28 E30 G27 E29 K23 H26 F30 L22 H27 G29 G30 M21 J24 J26 H30 L23 J29 K24 J30 M22 K29 N21 K25 L24 L27 L26 L28 L30 M27 M26 M29 N29 M30
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VirtexTM-E 1.8 V Extended Memory Field Programmable Gate Arrays Table 5: Bank 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 FG900 Fine-Pitch BGA Package -- XCV812E Description IO_L112P_YY IO_L112N_YY IO_D4_L113P_YY IO_VREF_L113N_YY IO_L114P IO_L114N IO_L115P IO_L115N IO_L116P_YY IO_L116N_YY IO_L117P_Y IO_VREF_L117N_Y IO_L118P IO_L118N IO_L120P IO_L120N IO_L121P_Y IO_L121N_Y IO_L123P_YY IO_D5_L123N_YY IO_D6_L124P_YY IO_VREF_L124N_YY IO_L125P IO_L125N IO_L126P IO_L126N IO_L127P IO_VREF_L127N IO_L128P IO_L128N IO_L129P_Y IO_L129N_Y IO_L130P_YY IO_L130N_YY Pin U25 V27 U24 V29 W30 U22 U21 W29 V26 W27 W26 Y29 W25 Y30 AA30 W24 AA29 V20 Y26 AB30 V21 AA28 Y25 AA27 W22 Y23 Y24 AB28 AC30 AA25 W21 AA24 AB26 AD30
Table 5: Bank 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
FG900 Fine-Pitch BGA Package -- XCV812E Description IO_L97P IO_L97N IO_VREF_L98P_YY IO_D3_L98N_YY IO_L99P_YY IO_L99N_YY IO_L100P_Y IO_L100N_Y IO_L101P IO_L101N IO_VREF_2_L102P IO_L102N IO_L104P IO_L104N IO_L106P Pin N25 N27 N30 P21 N26 P28 P29 N24 P22 R26 P25 R29 R25 T30 R24
3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
IO IO IO IO IO IO IO IO_L106N IO_L107P IO_L107N IO_L108P IO_L108N IO_L109P IO_VREF_L109N IO_L110P IO_L110N IO_L111P_Y IO_L111N_Y
T24 V24 Y21 Y27 AB27 AF28 AG30 U29 R22 T27 R23 T28 T21 T25 U28 U30 T23 U27
3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
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VirtexTM-E 1.8 V Extended Memory Field Programmable Gate Arrays Table 5: Bank 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 FG900 Fine-Pitch BGA Package -- XCV812E Description IO_L131P_YY IO_VREF_L131N_YY IO_L132P IO_L132N IO_L133P IO_L133N IO_L134P_YY IO_L134N_YY IO_L135P_Y IO_VREF_L135N_Y IO_L136P IO_L136N IO_L138P IO_L138N IO_L139P_Y IO_L139N_Y IO_D7_L141P_YY IO_INIT_L141N_YY Pin Y22 AC27 AD28 AB25 AC26 AE30 AD27 AF30 AF29 AB24 AB23 AE28 AE26 AG29 AH30 AC24 AH29 AA22 Table 5: Bank 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 GCK0 IO IO IO IO IO IO IO IO IO IO IO IO IO_VREF_4 IO_L142P_YY AJ16 AB19 AC16 AC19 AD19 AD20 AE21 AF19 AH17 AH23 AH26 AH27 AK18 AA18 AF27 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4
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FG900 Fine-Pitch BGA Package -- XCV812E Description IO_L142N_YY IO_L144P_Y IO_L144N_Y IO_L145P_Y IO_L145N_Y IO_L147P_YY IO_L147N_YY IO_VREF_4_L148P_YY IO_L148N_YY IO_L149P IO_L149N IO_L150P IO_L150N IO_L151P_YY IO_L151N_YY IO_VREF_4_L152P_YY IO_L152N_YY IO_L153P IO_L153N IO_L154P IO_L154N IO_L155P_YY IO_L155N_YY IO_VREF_4_L156P_YY IO_L156N_YY IO_L158P IO_L158N IO_L160P IO_L160N IO_L162P_Y IO_L162N_Y IO_L163P_Y IO_L163N_Y IO_L165P_YY Pin AK28 AD23 AJ27 AB21 AF25 AA21 AG25 AJ26 AD22 AA20 AH25 AC21 AF24 AG24 AK26 AJ24 AF23 AE23 AB20 AC20 AG23 AF22 AE22 AJ22 AG22 AA19 AF21 AG21 AK23 AE20 AJ21 AG20 AF20 AJ20
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VirtexTM-E 1.8 V Extended Memory Field Programmable Gate Arrays Table 5: Bank 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 FG900 Fine-Pitch BGA Package -- XCV812E Description IO_L179N IO_L180P_YY IO_VREF_5_L180N_YY IO_L181P_YY IO_L181N_YY IO_L182P IO_L182N IO_L183P IO_L183N IO_L184P_YY IO_VREF_5_L184N_YY IO_L185P_YY IO_L185N_YY IO_L186P IO_L186N IO_L187P IO_L187N IO_L188P_YY IO_VREF_5_L188N_YY IO_L189P_YY IO_L189N_YY IO_L191P_Y IO_L191N_Y IO_L192P_Y IO_L192N_Y IO_L194P_YY IO_L194N_YY IO_L195P_YY IO_VREF_5_L195N_YY IO_L196P IO_L196N IO_L197P IO_L197N IO_L198P_YY Pin AF15 AA15 AF14 AH15 AK15 AB14 AF13 AH14 AJ14 AE14 AG13 AK13 AD13 AE13 AF12 AC13 AA13 AA12 AJ12 AB12 AE11 AG11 AF11 AH11 AJ11 AD12 AK11 AJ10 AC12 AK10 AD11 AJ9 AE9 AH10
Table 5: Bank 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4
FG900 Fine-Pitch BGA Package -- XCV812E Description IO_L165N_YY IO_VREF_4_L166P_YY IO_L166N_YY IO_L167P IO_L167N IO_L168P IO_L168N IO_L169P_YY IO_L169N_YY IO_VREF_4_L170P_YY IO_L170N_YY IO_L171P IO_L171N IO_L172P IO_L172N IO_L173P_YY IO_L173N_YY IO_VREF_4_L174P_YY IO_L174N_YY IO_L176P IO_L176N IO_LVDS_DLL_L177P Pin AE19 AK22 AH20 AG19 AB17 AJ19 AD17 AA16 AA17 AK21 AB16 AG18 AK20 AK19 AD16 AE16 AE17 AG17 AJ17 AG16 AK17 AF16
5 5 5 5 5 5 5 5 5 5 5
GCK1 IO IO IO IO IO IO IO IO IO_LVDS_DLL_L177N IO_L179P
AK16 AD8 AD14 AE10 AE12 AG15 AH5 AH8 AK12 AH16 AB15
5 5 5 5 5 5 5 5 5 5 5
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VirtexTM-E 1.8 V Extended Memory Field Programmable Gate Arrays Table 5: Bank 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 FG900 Fine-Pitch BGA Package -- XCV812E Description IO_VREF_5_L198N_YY IO_L199P_YY IO_L199N_YY IO_L200P IO_L200N IO_L201P IO_L201N IO_L202P_YY IO_VREF_5_L202N_YY IO_L203P_YY IO_L203N_YY IO_L204P IO_L204N IO_L205P IO_L205N IO_L206P_YY IO_VREF_5_L206N_YY IO_L207P_YY IO_L207N_YY IO_L209P_Y IO_L209N_Y IO_L210P_Y IO_L210N_Y Pin AF9 AH9 AK9 AF8 AB11 AC11 AG8 AK8 AF7 AG7 AK7 AJ7 AD10 AH6 AC10 AD9 AG6 AB10 AJ5 AC9 AJ4 AG5 AK4 Table 5: Bank 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 IO IO IO IO IO IO IO IO IO IO T6 U1 U6 V7 V8 W10 Y10 AA2 AA4 AD1 6 6 6 6 6 6 6 6 6 6
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FG900 Fine-Pitch BGA Package -- XCV812E Description IO IO IO_L212N_YY IO_L212P_YY IO_L214N_Y IO_L214P_Y IO_L215N IO_L215P IO_L217N IO_L217P IO_VREF_L218N_Y IO_L218P_Y IO_L219N_YY IO_L219P_YY IO_L220N IO_L220P IO_L221N IO_L221P IO_VREF_L222N_YY IO_L222P_YY IO_L223N_YY IO_L223P_YY IO_L224N_Y IO_L224P_Y IO_L225N IO_L225P IO_VREF_L226N IO_L226P IO_L228N IO_L228P IO_VREF IO_L230N IO_L230P IO_L232N_Y Pin AD6 AG2 AF3 AC6 AB9 AE4 AE3 AH1 AG1 AA10 AA9 AD4 AD5 AD2 AD3 AF2 AA8 AA7 AF1 Y9 AB6 AC4 AE1 W8 Y8 AB4 AB3 W9 AB1 V10 AC1 V11 AA3 W7
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VirtexTM-E 1.8 V Extended Memory Field Programmable Gate Arrays Table 5: Bank 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 FG900 Fine-Pitch BGA Package -- XCV812E Description IO IO IO_L247P IO_L249N IO_L249P IO_L250N IO_L250P IO_L251N IO_VREF_L251P IO_L252N IO_L252P IO_L253N_Y IO_L253P_Y IO_L254N_YY IO_L254P_YY IO_L255N_YY IO_VREF_L255P_YY IO_L256N IO_L256P IO_L257N IO_L257P IO_L258N_YY IO_L258P_YY IO_L259N_Y IO_VREF_L259P_Y IO_L260N IO_L260P IO_L262N IO_L262P IO_L263N_Y IO_L263P_Y IO_L265N_YY IO_L265P_YY IO_L266N_YY Pin N8 R5 R10 R8 R4 R7 R3 P10 P6 P5 P2 P7 P4 N4 R2 N7 P1 M6 N6 N5 N1 M4 M5 M2 M1 L4 L2 L1 M8 K2 M9 K5 K1 L6
Table 5: Bank 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6
FG900 Fine-Pitch BGA Package -- XCV812E Description IO_L232P_Y IO_L233N IO_L233P IO_L235N IO_L235P IO_VREF_L236N_Y IO_L236P_Y IO_L237N_YY IO_L237P_YY IO_L238N IO_L238P IO_L239N IO_L239P IO_VREF_L240N_YY IO_L240P_YY IO_L241N_YY IO_L241P_YY IO_L242N_Y IO_L242P_Y IO_L243N IO_L243P IO_VREF_L244N IO_L244P IO_L246N IO_L246P IO_L247N Pin AA6 Y6 Y4 Y3 Y2 Y5 W5 W4 W6 V6 W2 U9 V4 AB2 T8 U5 W1 Y1 T9 T7 U3 T5 V2 T4 U2 T1
7 7 7 7 7 7 7
IO IO IO IO IO IO IO
D1 E3 J4 J6 K10 L3 M7
7 7 7 7 7 7 7
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VirtexTM-E 1.8 V Extended Memory Field Programmable Gate Arrays Table 5: Bank 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 FG900 Fine-Pitch BGA Package -- XCV812E Description IO_VREF_L266P_YY IO_L267N IO_L267P IO_L268N IO_L268P IO_L269N IO_VREF_L269P IO_L270N IO_L270P IO_L271N_Y IO_L271P_Y IO_L272N_YY IO_L272P_YY IO_L273N_YY IO_VREF_L273P_YY IO_L274N IO_L274P IO_L275N IO_L275P IO_L276N_YY IO_L276P_YY IO_L277N_Y IO_VREF_L277P_Y IO_L278N IO_L278P IO_L280N IO_L280P IO_L281N_Y IO_L281P_Y Pin K3 L7 K4 L8 J5 K6 H4 H1 K7 J7 J2 H5 G2 L9 G5 F3 K8 G3 E1 H6 E2 E4 K9 J8 F4 G6 C2 D2 F5 NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA 2 NA NA 3 DONE DXN DXP CCLK AJ28 AJ3 AH4 F26 NA NA NA NA VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT L11 L12 L19 L20 M11 M12 M19 M20 N13 N14 N15 N16 N17 N18 P13 P18 R13 R18 T13 T18 U18 U13 V13 V14 V15 Table 5: Bank NA NA NA NA NA NA 2 NA
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FG900 Fine-Pitch BGA Package -- XCV812E Description M0 M1 M2 PROGRAM TCK TDI TDO TMS Pin AF4 AC7 AK3 AG28 B3 H22 D26 C1
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VirtexTM-E 1.8 V Extended Memory Field Programmable Gate Arrays Table 5: Bank NA NA NA NA NA NA NA NA NA NA NA NA FG900 Fine-Pitch BGA Package -- XCV812E Description VCCO_2 VCCO_2 VCCO_3 VCCO_3 VCCO_3 VCCO_3 VCCO_3 VCCO_3 VCCO_3 VCCO_3 VCCO_4 VCCO_4 VCCO_4 VCCO_4 VCCO_4 VCCO_4 VCCO_4 VCCO_4 VCCO_5 VCCO_5 VCCO_5 VCCO_5 VCCO_5 VCCO_5 VCCO_5 VCCO_5 VCCO_6 VCCO_6 VCCO_6 VCCO_6 VCCO_6 VCCO_6 VCCO_6 VCCO_6 Pin N19 P19 AE29 W28 U23 U20 T20 V19 T19 U19 AJ25 AH19 W18 AC17 Y17 W17 W16 Y16 AJ6 Y15 W15 AC14 Y14 W14 W13 AH12 AE2 V12 U12 T12 U11 T11 U8 W3
Table 5: Bank NA NA NA NA NA NA NA NA NA NA NA
FG900 Fine-Pitch BGA Package -- XCV812E Description VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT Pin V16 V17 V18 W11 W12 W19 W20 Y11 Y12 Y19 Y20
NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA
VCCO_0 VCCO_0 VCCO_0 VCCO_0 VCCO_0 VCCO_0 VCCO_0 VCCO_0 VCCO_1 VCCO_1 VCCO_1 VCCO_1 VCCO_1 VCCO_1 VCCO_1 VCCO_1 VCCO_2 VCCO_2 VCCO_2 VCCO_2 VCCO_2 VCCO_2
B6 M15 M14 L15 L14 H14 M13 C12 B25 C19 M18 M17 L17 H17 L16 M16 F29 M28 P23 R20 P20 R19
NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA
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VirtexTM-E 1.8 V Extended Memory Field Programmable Gate Arrays Table 5: Bank NA NA NA NA NA NA NA NA FG900 Fine-Pitch BGA Package -- XCV812E Description VCCO_7 VCCO_7 VCCO_7 VCCO_7 VCCO_7 VCCO_7 VCCO_7 VCCO_7 Pin F2 R12 P12 N12 R11 P11 P8 M3 Table 5: Bank NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND Y18 AH7 AK30 AJ30 B30 A30 AK29 AJ29 AC29 H29 B29 A29 AH28 V28 N28 C28 AG27 D27 AF26 E26 F25 AE25 G24 AJ23 AD24 NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA
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FG900 Fine-Pitch BGA Package -- XCV812E Description GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND Pin H23 B23 AC23 AB22 V22 N22 AH18 AB18 J18 C18 U17 T17 R17 P17 U16 T16 R16 P16 U15 T15 R15 P15 U14 T14 R14 P14 AH13 AB13 J13 C13 V9 N9 J9 AJ8
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VirtexTM-E 1.8 V Extended Memory Field Programmable Gate Arrays
Table 5: Bank NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA
FG900 Fine-Pitch BGA Package -- XCV812E Description GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND Pin AC8 H8 AD7 B8 AE6 G7 F6 AF5 E5 AG4 D4 V3 N3 C3 AK2 AH3 AC2 H2 B2 A2 AK1 AJ2 AJ1 A1 B1
FG900 Differential Pin Pairs
Virtex-E Extended Memory devices have differential pin pairs that can also provide other functions when not used as a differential pair. A in the AO column indicates that the pin pair can be used as an asynchronous output for all devices provided in this package. Pairs with a note number in the AO column are device dependent. They can have asynchronous outputs if the pin pair is in the same CLB row and column in the device. Numbers in this column refer to footnotes that indicate which devices have pin pairs that can be asynchronous outputs. The Other Functions column indicates alternative function(s) not available when the pair is used as a differential pair or differential clock. Table 6: FG900 Differential Pin Pair Summary -- XCV812E P Pair 3 2 1 0 Bank 0 1 5 4 Pin C15 E15 AK16 AJ16 N Pin A15 E16 AH16 AF16 AO NA NA NA NA GCLK LVDS IO LVDS 34 IO LVDS 34 IO LVDS 177 IO LVDS 177 Other Functions
IO LVDS Total Pairs: 235, Asynchronous Output Pairs: 85 1 2 4 5 6 7 8 9 10 11 12 13 15 17 19 20 22 23 24 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 G8 H9 D6 B5 F8 N11 E8 J11 B7 H10 F10 H11 J12 B10 F11 D11 C11 D12 A11 D5 A3 A4 E7 A5 D7 G9 A6 C7 C8 G10 A8 B9 G11 H13 E11 F12 A10 E12 VREF VREF VREF VREF -
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VirtexTM-E 1.8 V Extended Memory Field Programmable Gate Arrays Table 6: FG900 Differential Pin Pair Summary -- XCV812E P Pair 25 26 27 28 29 30 31 34 35 36 37 38 39 40 41 42 43 44 45 46 48 49 51 52 53 54 55 56 57 58 59 60 61 62 63 64 66 Bank 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Pin B12 K13 B13 E13 B14 J14 J15 E16 F16 H16 K15 G16 E17 C17 A18 A19 G18 H18 F19 K17 C20 E20 A21 A22 B22 D22 C22 E22 A23 K19 B24 G22 C25 A26 K20 J21 G23 N Pin G13 A12 F13 G14 D14 A14 K14 A15 B16 A16 C16 K16 A17 F17 E18 D18 B19 D19 F18 B20 G19 K18 F20 C21 H19 E21 F21 H20 G21 A24 C24 H21 E23 D24 B26 D25 B27 AO Other Functions VREF VREF GCLK LVDS 3/2 VREF VREF VREF VREF VREF VREF VREF Pair 67 69 70 72 73 75 76 77 78 79 80 81 82 83 84 86 88 90 91 93 94 95 96 97 98 99 100 101 102 104 106 107 108 109 110 111 112 Bank 1 1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 3 3 3 3 3 3 3 Table 6: FG900 Differential Pin Pair Summary -- XCV812E P Pin F24 C27 J22 G25 E28 D30 L21 G28 G27 K23 F30 H27 G30 J24 H30 J29 M22 N21 L24 L26 L30 M26 N29 N25 N30 N26 P29 P22 P25 R25 R24 R22 R23 T21 U28 T23 U25 N Pin A27 K21 E27 E25 C30 J23 F28 E30 E29 H26 L22 G29 M21 J26 L23 K24 K29 K25 L27 L28 M27 M29 M30 N27 P21 P28 N24 R26 R29 T30 U29 T27 T28 T25 U30 U27 V27 AO Other Functions CS DIN_D0 VREF VREF VREF D2 VREF D3 VREF TRDY VREF -
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VirtexTM-E 1.8 V Extended Memory Field Programmable Gate Arrays Table 6: FG900 Differential Pin Pair Summary -- XCV812E P Pair 156 158 160 162 163 165 166 167 168 169 170 171 172 173 174 176 177 179 180 181 182 183 184 185 186 187 188 189 191 192 194 195 196 197 198 199 200 Bank 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 Pin AJ22 AA19 AG21 AE20 AG20 AJ20 AK22 AG19 AJ19 AA16 AK21 AG18 AK19 AE16 AG17 AG16 AF16 AB15 AA15 AH15 AB14 AH14 AE14 AK13 AE13 AC13 AA12 AB12 AG11 AH11 AD12 AJ10 AK10 AJ9 AH10 AH9 AF8 N Pin AG22 AF21 AK23 AJ21 AF20 AE19 AH20 AB17 AD17 AA17 AB16 AK20 AD16 AE17 AJ17 AK17 AH16 AF15 AF14 AK15 AF13 AJ14 AG13 AD13 AF12 AA13 AJ12 AE11 AF11 AJ11 AK11 AC12 AD11 AE9 AF9 AK9 AB11 AO Other Functions VREF VREF VREF VREF GCLK LVDS 1/0 VREF VREF VREF VREF VREF -
Table 6:
FG900 Differential Pin Pair Summary -- XCV812E P N Pin V29 U22 W29 W27 Y29 Y30 W24 V20 AB30 AA28 AA27 Y23 AB28 AA25 AA24 AD30 AC27 AB25 AE30 AF30 AB24 AE28 AG29 AC24 AA22 AK28 AJ27 AF25 AG25 AD22 AH25 AF24 AK26 AF23 AB20 AG23 AE22 AO Other Functions VREF VREF D5 VREF VREF VREF VREF INIT VREF VREF Pin U24 W30 U21 V26 W26 W25 AA30 AA29 Y26 V21 Y25 W22 Y24 AC30 W21 AB26 Y22 AD28 AC26 AD27 AF29 AB23 AE26 AH30 AH29 AF27 AD23 AB21 AA21 AJ26 AA20 AC21 AG24 AJ24 AE23 AC20 AF22
Pair 113 114 115 116 117 118 120 121 123 124 125 126 127 128 129 130 131 132 133 134 135 136 138 139 141 142 144 145 147 148 149 150 151 152 153 154 155
Bank 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 4 4 4 4 4 4 4 4 4 4 4 4
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VirtexTM-E 1.8 V Extended Memory Field Programmable Gate Arrays Table 6: FG900 Differential Pin Pair Summary -- XCV812E P Pair 201 202 203 204 205 206 207 209 210 212 214 215 217 218 219 220 221 222 223 224 225 226 228 230 232 233 235 236 237 238 239 240 241 242 243 244 246 Bank 5 5 5 5 5 5 5 5 5 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 Pin AC11 AK8 AG7 AJ7 AH6 AD9 AB10 AC9 AG5 AC6 AE4 AH1 AA10 AD4 AD2 AF2 AA7 Y9 AC4 W8 AB4 W9 V10 AA3 AA6 Y4 Y2 W5 W6 W2 V4 T8 W1 T9 U3 V2 U2 N Pin AG8 AF7 AK7 AD10 AC10 AG6 AJ5 AJ4 AK4 AF3 AB9 AE3 AG1 AA9 AD5 AD3 AA8 AF1 AB6 AE1 Y8 AB3 AB1 V11 W7 Y6 Y3 Y5 W4 V6 U9 AB2 U5 Y1 T7 T5 T4 AO Other Functions VREF VREF VREF VREF VREF VREF VREF VREF Pair 247 249 250 251 252 253 254 255 256 257 258 259 260 262 263 265 266 267 268 269 270 271 272 273 274 275 276 277 278 280 281 Bank 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 Table 6: FG900 Differential Pin Pair Summary -- XCV812E P Pin R10 R4 R3 P6 P2 P4 R2 P1 N6 N1 M5 M1 L2 M8 M9 K1 K3 K4 J5 H4 K7 J2 G2 G5 K8 E1 E2 K9 F4 C2 F5 N Pin T1 R8 R7 P10 P5 P7 N4 N7 M6 N5 M4 M2 L4 L1 K2 K5 L6 L7 L8 K6 H1 J7 H5 L9 F3 G3 H6 E4 J8 G6 D2 AO Other Functions IRDY VREF VREF VREF VREF VREF VREF VREF -
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VirtexTM-E 1.8 V Extended Memory Field Programmable Gate Arrays
Virtex-E Extended Memory Device/Package Combinations and Maximum I/O
Virtex-E Extended Memory Series Maximum User I/O by Device/Package (Excluding Dedicated Clock Pins) Package BG560 FG676 FG900 XCV405E 404 404 556 XCV812E 404
Virtex-E Ordering Information
Virtex-II ordering information is shown in Figure 1
Example: XCV405E-6BG560C
Device Type Temperature Range C = Commercial (TJ = 0C to +85C) I = Industrial (TJ = -40C to +100C) Number of Pins Package Type BG = Ball Grid Array FG = Fine Pitch Ball Grid Array
DS025_001_112000
Speed Grade (-6, -7, -8)
Figure 1: Virtex Ordering Information
DS025-4 (v1.6) July 17, 2002
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VirtexTM-E 1.8 V Extended Memory Field Programmable Gate Arrays
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Revision History
The following table shows the revision history for this document. Date 03/23/00 08/01/00 09/19/00 Version 1.0 1.1 1.2 Initial Xilinx release. Accumulated edits and fixes. Upgrade to Preliminary. Preview -8 numbers added. Reformatted to adhere to corporate documentation style guidelines. Minor changes in BG560 pin-out table. * * * * * * * 04/02/01 1.4 * * * 07/23/01 07/17/02 1.5 1.6 * * In Table 3 (Module 4), FG676 Fine-Pitch BGA -- XCV405E, the following pins are no longer labeled as VREF: B7, G16, G26, W26, AF20, AF8, Y1, H1. Min values added to Virtex-E Electrical Characteristics tables. Updated speed grade -8 numbers in Virtex-E Electrical Characteristics tables (Module 3). Updated minimums in Table 11 (Module 2), and added notes to Table 12 (Module 2). Added to note 2 of Absolute Maximum Ratings (Module 3). Changed all minimum hold times to -0.4 for Global Clock Set-Up and Hold for LVTTL Standard, with DLL (Module 3). Revised maximum TDLLPW in -6 speed grade for DLL Timing Parameters (Module 3). In Table 4, FG676 Fine-Pitch BGA -- XCV405E, pin B19 is no longer labeled as VREF, and pin G16 is now labeled as VREF. Updated values in Virtex-E Switching Characteristics tables. Converted data sheet to modularized format. See the Virtex-E Extended Memory Data Sheet section. Changed definition of T31 and T32 pins in Table 1 for XCV405E and the XCV812E devices. Data sheet designation upgraded from Preliminary to Production. Revision
11/20/00
1.3
Virtex-E Extended Memory Data Sheet
The Virtex-E Extended Memory Data Sheet contains the following modules: * * DS025-1, Virtex-E 1.8V Extended Memory FPGAs:
Introduction and Ordering Information (Module 1)
* *
DS025-3, Virtex-E 1.8V Extended Memory FPGAs:
DC and Switching Characteristics (Module 3)
DS025-2, Virtex-E 1.8V Extended Memory FPGAs:
Functional Description (Module 2)
DS025-4, Virtex-E 1.8V Extended Memory FPGAs:
Pinout Tables (Module 4)
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